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FAILURE-SENSITIVE ANALYSIS OF PARALLEL algorithmS WITH CONTROLLED MEMORY ACCESS CONCURRENCY

PARALLEL PROCESSING LETTERS 2007年第2期17卷 153-168页

作者： Georgiou, Chryssis Russell, Alexander Shvartsman, Alexander A. Univ Cyprus Dept Comp Sci 75 Kallipoleos Str CY-1678 Nicosia Cyprus Univ Connecticut Comp Sci & Engn Storrs CT 06269 USA

The abstract problem of using P failure-prone processors to cooperatively update all locations of an iV-element shared array is called Write-AU. Solutions to Write-All can be used iteratively to construct efficient simulations of PRAM algorithms on failureprone PRAMS. Such use of Write-All in simulations is abstracted in terms of the iterative Write-All problem. The efficiency of the algorithmic solutions for Write-Aii and iterative Write-All is measured in terms of work complexity where all processing steps taken by the processors are counted. This paper considers determinitic solutions for the WriteA1I and iterative Write-All problems in the fail-stop synchronous CRCW PRAM model where memory access concurrency needs to be controlled. A deterministic algorithm of Kanellakis, Michailidis, and Shvartsman [16] efficiently solves the Write-All problem in this model, while controlling read and write memory access concurrency. However it was not shown how the number of processor failures / affects the work efficiency of the algorithm. The results herein give a new analysis of the algorithm [16] that obtain failure-sensitive work bounds, while retaining the known memory access concurrency bounds. Specifically, the new result expresses the work bound as a function of N, P and f. Another contribution in this paper is the new failure-sensitive analysis for iterative Write-All with controlled memory access concurrency. This result yields tighter bounds on work (vs. [16]) for simulations of PRAM algorithms on fail-stop PRAMS.

关键词： Parallel algorithms work complexity fault-tolerance algorithm simulations memory access concurrency

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