High Level Synthesis for Systems on Chip is a challenging way to cut off development time, while assuming a good level of performance. But the HLS tools are limited by the abstraction level of the description to perfo...
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ISBN:
(纸本)9781479911707
High Level Synthesis for Systems on Chip is a challenging way to cut off development time, while assuming a good level of performance. But the HLS tools are limited by the abstraction level of the description to perform some high level transforms. This paper evaluates the impact of such high level transforms for ASICs. We have evaluated recursive and non recursive filters for signal processing an morphological filters for image processing. We show that the impact of HLTs to reduce energy consumption is high : from x3.4 for one 1D filter up to x5.6 for cascaded 1D filters and about x3.5 for morphological 2D filters.
In this paper, we present low-power reconfigurable adaptive equalizers derived via dynamic algorithm transforms (DAT's). The principle behind DAT is that conventional signal processing systems are designed for the...
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In this paper, we present low-power reconfigurable adaptive equalizers derived via dynamic algorithm transforms (DAT's). The principle behind DAT is that conventional signal processing systems are designed for the worst case and are not energy-optimum on average. Therefore, significant energy savings can be achieved by optimally reconfiguring the hardware in these situations. Practical reconfiguration strategies for adaptive filters are-presented. These strategies are derived as a solution to an optimization problem. The optimization problem has energy as the objective function and a constraint on the algorithm performance (specifically the SNR), The DAT-based adaptive filter is employed as an equalizer for a 51.84 Mb/s very-high-speed digital subscriber loop (VDSL) over 24-pair BKMA cable. The channel nonstationarities are due to variations in cable length and number of far-end crosstalk (FEXT) interferers. For this application,:the traditional design is based on 1 kft cable length and 11 FEXT interferers. Tt was found that up to 81% energy savings can be achieved when cable length varies from 1-0.1 kft and the number of FEXT interferers varies from 11 to 4, On the average, 53% energy savings are achieved as compared with the conventional worst-case design.
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