检索结果-内蒙古大学图书馆

MODIFYING REAL CONVOLUTIONAL-CODES FOR PROTECTING DIGITAL FILTERING SYSTEMS

IEEE TRANSACTIONS ON INFORMATION THEORY 1993年第2期39卷 553-564页

作者： REDINBO, GR ZAGAR, B GRAZ TECH UNIV INST ALLEGEMEINE ELEKTROTECH & ELEKT MESSTECHA-8010 GRAZAUSTRIA

Digital filters when implemented with very dense high-speed electronic devices are susceptible to both temporary and permanent failures, not easily protected by conventional fault-tolerant computer design principles. A new method is presented for protecting the overall realization against both hard and soft errors at the data sample level using the error-detecting properties of real convolutional codes. The normal filter system is surrounded with parallel parity channels defined by a real systematic convolutional code. Erroneous behavior is detected by comparing externally the calculated and regenerated parity samples. A rate k/n real convolutional code produces (n - k) parity samples for every k input samples causing the parity channels to operate at a rate decimated by k. Significant complexity reductions are possible by modifying the code structure, without loss of error protection, yielding simplified parity channels with finite impulse response (FIR) structures with computational rates decimated by k. The code modification procedure determines k nonzero scaling coefficients for weighting respective rows of the convolutional code's generator matrix. A matrix equation involving the code's original parity values and the denominator polynomial of the digital filter's transfer function is formed. Row manipulations separate this equation into two parts, a set of homogeneous equations constraining the modifying scaling coefficients and another set defining the implementation of the code parity values. An annihilator subspace in the dual space related to a condensed matrix defines the family of acceptable scaling coefficients when the code parameter k is less then the number of parity values, (n - k), times the number of poles in the filter. The code modification process has been automated in a computer algorithm. The effects of parity filter quantizations are analyzed and a bound on the mean-square error in the parity comparisons is given.

关键词： REAL CONVOLUTIONAL CODES fault-TOLERANT PROCESSING algorithm-based fault tolerance PROTECTING DIGITAL FILTERING ANNIHILATOR SUBSPACES

来源：评论

学校读者我要写书评

暂无评论

DIAGNOSABILITY AND DIAGNOSIS OF algorithm-based fault-TOLERANT SYSTEMS

引用

IEEE TRANSACTIONS ON COMPUTERS 1993年第8期42卷 924-937页

作者： VINNAKOTA, B JHA, NK PRINCETON UNIV DEPT ELECT ENGN PRINCETON NJ 08544 USA

Parallel processing architectures are now in common use for signal processing and other computation-intensive applications. These applications are characterized by high throughput and long processing periods. Such characteristics decrease the reliability of high-performance architectures. The erroneous data produced by faulty processors could have damaging consequences, particularly in critical real-time applications. It is therefore desirable that any erroneous data produced by the system be detected and located as quickly as possible. algorithm-based fault tolerance (ABFT) is a low-cost system-level concurrent error detection and fault location scheme. We apply methods used in the analysis of multiprocessor systems employing system-level diagnosis to the analysis of ABFT systems. A new algorithm to analyze an ABFT system for its fault diagnosability is developed using these methods. based on this work, a fault diagnosis algorithm is developed for ABFT systems. No such algorithm has been presented previously.

关键词： algorithm-based fault tolerance CHECKSUM ENCODING CONCURRENT ERROR DETECTION CONCURRENT fault DIAGNOSIS fault DIAGNOSABILITY

来源：评论

学校读者我要写书评

暂无评论

fault-TOLERANT VLSI SYSTEMS

引用

PROCEEDINGS OF THE IEEE 1993年第5期81卷 745-758页

作者： PEERCY, M BANERJEE, P Coordinated Sci. Lab. Illinois Univ. Urbana IL

This paper examines the wide variety of fault tolerance techniques applied to VLSI technology. We provide a brief synopsis of fault models at the device, gate, and function levels. Then, we introduce the basic methods available to the designer of fault tolerance measures by surveying redundancy techniques. The majority of this paper discusses fault detection, which is the discovery of a fault before it delivers errant data to the rest of the system. We examine techniques of fault detection that use space, time, and information redundancies. Along with these redundancy measures, we also investigate algorithm-based fault tolerance in VLSI components. After discussing large-scale processor-level implementations of fault detection, we describe fault tolerance in automated VLSI production systems. After our treatment of the detection of errors and faults, we examine the other areas of fault tolerance in VLSI: reconfiguration of the system and recovery of system operation. We look into the issues involved in reconfiguration after discovery of a fault in fabrication or in operation. Our time here is spent generally in VLSI arrays. We conclude our discussion of fault tolerance in VLSI with an overview of the on-chip recovery capabilities of a VLSI microprocessor.

关键词： VLSI VLSI systems algorithm-based fault tolerance automated VLSI production systems circuit reliability error detection fault detection fault models fault tolerance techniques fault tolerant computing microprocessor microprocessor chips reconfiguration redundancy redundancy techniques system recovery

来源：评论

学校读者我要写书评

暂无评论

EVALUATION AND COMPARISON OF fault-TOLERANT SOFTWARE TECHNIQUES

引用

IEEE TRANSACTIONS ON RELIABILITY 1993年第2期42卷 190-204页

作者： HUDAK, J SUH, BH SIEWIOREK, D SEGALL, Z CARNEGIE MELLON UNIV DEPT ELECT & COMP ENGNPITTSBURGHPA 15213

Various fault-tolerant software techniques have been proposed in order to meet the reliability requirements of critical systems. This paper evaluates 4 implementations of fault-tolerant software techniques with respect to hardware and design faults. Project participants were divided into 4 groups, each of which developed fault-tolerant software based on a common specification. Each group applied one of the following techniques: n-version programming, recovery block, concurrent error-detection, and algorithm-based fault tolerance. Independent testing and modeling groups within the project then thoroughly analyzed the fault-tolerant software. Using fault-injection tools, the testing group subjected the fault-tolerant software to simulated design and hardware faults. Simulated design-faults included control flow, array boundary, computational, and post/pre increment/decrement software mutations. Simulated hardware-faults included code and data corruption. Data collected from the fault-injection experiment were then mapped into a discrete-time Markov model developed by the modeling group. based on this model, the effectiveness of each implementation of the fault-tolerant software technique with respect to availability, correctness, and time to failure given an error, is contrasted with measured data. Finally, the model is analyzed with respect to additional figures of merit identified during the modeling process, and the techniques are ranked using an application taxonomy.

关键词： fault-TOLERANT SOFTWARE N-VERSION PROGRAMMING RECOVERY BLOCK CONCURRENT ERROR-DETECTION algorithm-based fault tolerance MARKOV MODEL fault-INJECTION TESTING

来源：评论

学校读者我要写书评

暂无评论

OPTIMAL-DESIGN OF CHECKS FOR ERROR-DETECTION AND LOCATION IN fault-TOLERANT MULTIPROCESSOR SYSTEMS

引用

IEEE TRANSACTIONS ON COMPUTERS 1993年第7期42卷 780-793页

作者： SITARAMAN, RK JHA, NK PRINCETON UNIV DEPT ELECT ENGNPRINCETONNJ 08544

Designing checks to detect or locate errors in the data plays an important role in the design of fault tolerant systems. Recently, the problem of synthesizing the data-check (DC) relationship has received a lot of attention in the context of a natural paradigm for concurrent error detection/location known as algorithm-based fault tolerance (ABFT). Banerjee and Abraham have shown that an ABFT scheme can be modeled as a tripartite graph consisting of processors (P), data (D), and checks (C). Any technique for designing ABFT systems requires a procedure for synthesizing a DC relationship, which not only has a low overhead but also has all the properties required by the designer. The main contribution of this work is to propose a simple and novel algorithm called RANDGEN to generate DC graphs. This synthesis approach itself is very fast and can be fully parallelized. By simply varying its parameters, the same algorithm RANDGEN can produce DC graphs with a wide spectrum of properties, many of which have been considered very important in recent ABFT designs. RANDGEN produces s-error-detectable DC graphs with asymptotically the least number of checks for the first time. RANDGEN can also produce s-error-locatable DC graphs using only a small number of checks. This is the first general procedure for producing error-locatable graphs for any value of s. Another important outstanding problem in DC graph design is providing fast and practical methods for actually locating the errors in the data from the output pattern at the checks. We show that RANDGEN can be used to design DC graphs, which permit easy diagnosis, again with a small number of checks. It has been pointed out previously that ''uniform'' checks may simplify the design of the ABFT system. We show how RANDGEN can be modified very simply to produce uniform s-error-detectable/locatable DC graphs. Finally, we show how one can generalize these results to synthesize strictly s-error-detectable/locatable DC graphs which ca

关键词： algorithm-based fault tolerance CHECKSUM ENCODING CONCURRENT ERROR DETECTION CONCURRENT ERROR LOCATION MAJORITY DIAGNOSIS RANDOMIZED algorithmS UNIFORM CHECKS

来源：评论

学校读者我要写书评

暂无评论

SYNTHESIS OF algorithm-based fault-TOLERANT SYSTEMS FOR DEPENDENCE GRAPHS

引用

IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 1993年第8期4卷 864-874页

作者： VINNAKOTA, B JHA, NK PRINCETON UNIV DEPT ELECT ENGNPRINCETONNJ 08544

algorithm-based fault tolerance (ABFT) is a scheme to improve the reliability of parallel architectures used for computation-intensive tasks. The exact implementation of an ABFT scheme is algorithm-dependent. ABFT systems have very low overhead compared to other fault tolerance schemes with similar benefits. Few results are available in the area of general synthesis of ABFT systems. A two-stage approach to the synthesis of ABFT systems is proposed. In the first stage a system-level code is chosen to encode the data used in the algorithm. In the second stage the optimal architecture to implement the scheme is chosen using dependence graphs. Dependence graphs are a graph-theoretic form of algorithm representation. We demonstrate that not all architectures are ideal for the implementation of a particular ABFT scheme. We propose new measures to characterize the fault tolerance capability of a system to better exploit the proposed synthesis method. Dependence graphs can also be used for the synthesis of ABFT schemes for non-linear problems. An example of a fault-tolerant median filter is provided to illustrate their utility for such problems.

关键词： algorithm-based fault tolerance CHECKSUM ENCODING CONCURRENT ERROR DETECTION DEPENDENCE GRAPHS fault DETECTABILITY fault LOCATABILITY SYSTEM SYNTHESIS FOR fault tolerance

来源：评论

学校读者我要写书评

暂无评论

PROBABILISTIC EVALUATION OF ONLINE CHECKS IN fault-TOLERANT MULTIPROCESSOR SYSTEMS

引用

IEEE TRANSACTIONS ON COMPUTERS 1992年第5期41卷 532-541页

作者： NAIR, VSS HOSKOTE, YV ABRAHAM, JA UNIV TEXAS COMP ENGN RES CTR AUSTIN TX 78758 USA

The analysis of fault-tolerant multiprocessor systems that use concurrent error detection (CED) schemes is much more difficult than the analysis of conventional fault-tolerant architectures. Various analytical techniques have been proposed to evaluate CED schemes deterministically. However, these approaches are based on worst-case assumptions related to the failure of system components. Often, the evaluation results do not reflect the actual fault tolerance capabilities of the system. In this paper, we develop a probabilistic approach to evaluate the fault detecting and locating capabilities of on-line checks in a system. The various probabilities associated with the checking schemes are identified and used in the framework of the matrix-based model [1]. based on these probabilistic matrices, estimates for the fault tolerance capabilities of various systems are derived analytically.

关键词： algorithm-based fault tolerance CONCURRENT ERROR DETECTION fault COVERAGE LOCATABILITY PROBABILISTIC TECHNIQUES

来源：评论

学校读者我要写书评

暂无评论

A WELL CONDITIONED CHECKSUM SCHEME FOR algorithmIC fault tolerance

引用

INTEGRATION-THE VLSI JOURNAL 1991年第1期12卷 21-32页

作者： BOLEY, DL LUK, FT CORNELL UNIV SCH ELECT ENGN ITHACA NY 14853 USA

The weighted checksum scheme has been proposed as a low-cost fault tolerant procedure for parallel matrix computations. To guarantee multiple error detection and correction, the chosen weight vectors must satisfy some very specific properties about linear independence. However, previous weight generating methods that fulfill the independence criteria have troubles with numerical overflow. We will present a new scheme that generates weight vectors via Chebyshev polynomials to meet the requirements about independence and to avoid the difficulties with overflow.

关键词： algorithm-based fault tolerance CHEBYSHEV POLYNOMIALS LANCZOS algorithm BERLEKAMP-MASSEY algorithm

来源：评论

学校读者我要写书评

暂无评论

algorithm-based fault tolerance FOR MATRIX OPERATIONS

引用

IEEE TRANSACTIONS ON COMPUTERS 1984年第6期33卷 518-528页

作者： HUANG, KH ABRAHAM, JA UNIV ILLINOIS COORDINATED SCI LABURBANAIL 61801

The rapid progress in VLSI technology has reduced the cost of hardware, allowing multiple copies of low-cost processors to provide a large amount of computational capability for a small cost. In addition to achieving high performance, high reliability is also important to ensure that the results of long computations are valid. This paper proposes a novel system-level method of achieving high reliability, called algorithm-based fault tolerance. The technique encodes data at a high level, and algorithms are designed to operate on encoded data and produce encoded output data. The computation tasks within an algorithm are appropriately distributed among multiple computation units for fault tolerance. The technique is applied to matrix compomations which form the heart of many computation-intensive tasks. algorithm-based fault tolerance schemes are proposed to detect and correct errors when matrix operations such as addition, multiplication, scalar product, LU-decomposition, and transposition are performed using multiple processor systems. The method proposed can detect and correct any failure within a single processor in a multiple processor system. The number of processors needed to just detect errors in matrix multiplication is also studied.

关键词： algorithm-based fault tolerance checksum matrix error correction error detection matrix operations multiple processor systems processor arrays systolic arrays transient errors

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：