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PROBABILISTIC EVALUATION OF ONLINE CHECKS IN fault-TOLERANT MULTIPROCESSOR SYSTEMS

IEEE TRANSACTIONS ON COMPUTERS 1992年第5期41卷 532-541页

作者： NAIR, VSS HOSKOTE, YV ABRAHAM, JA UNIV TEXAS COMP ENGN RES CTR AUSTIN TX 78758 USA

The analysis of fault-tolerant multiprocessor systems that use concurrent error detection (CED) schemes is much more difficult than the analysis of conventional fault-tolerant architectures. Various analytical techniques have been proposed to evaluate CED schemes deterministically. However, these approaches are based on worst-case assumptions related to the failure of system components. Often, the evaluation results do not reflect the actual fault tolerance capabilities of the system. In this paper, we develop a probabilistic approach to evaluate the fault detecting and locating capabilities of on-line checks in a system. The various probabilities associated with the checking schemes are identified and used in the framework of the matrix-based model [1]. based on these probabilistic matrices, estimates for the fault tolerance capabilities of various systems are derived analytically.

关键词： algorithm-based fault tolerance CONCURRENT ERROR DETECTION fault COVERAGE LOCATABILITY PROBABILISTIC TECHNIQUES

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DESIGN OF algorithm-based fault-TOLERANT MULTIPROCESSOR SYSTEMS FOR CONCURRENT ERROR-DETECTION AND fault-DIAGNOSIS

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IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS 1994年第10期5卷 1099-1106页

作者： VINNAKOTA, B JHA, NK PRINCETON UNIV DEPT ELECT ENGNPRINCETONNJ 08544

algorithm-based fault tolerance (ABFT) is a low-overhead system-level concurrent error detection and fault location scheme for multiprocessor systems. In this short note, we present new methods for the design of ABFT systems. Our design procedure is applicable to a wide range of systems in which processors share data elements. A feature of our design approach is that the type of checks to be used in the final system can be controlled by the system designer. We also present some new bounds on the number of checks needed in ABFT system design.

关键词： algorithm-based fault tolerance CONCURRENT ERROR DETECTION fault DETECTABILITY fault DIAGNOSABILITY SYSTEM-LEVEL fault tolerance

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OPTIMAL-DESIGN OF CHECKS FOR ERROR-DETECTION AND LOCATION IN fault-TOLERANT MULTIPROCESSOR SYSTEMS

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IEEE TRANSACTIONS ON COMPUTERS 1993年第7期42卷 780-793页

作者： SITARAMAN, RK JHA, NK PRINCETON UNIV DEPT ELECT ENGNPRINCETONNJ 08544

Designing checks to detect or locate errors in the data plays an important role in the design of fault tolerant systems. Recently, the problem of synthesizing the data-check (DC) relationship has received a lot of attention in the context of a natural paradigm for concurrent error detection/location known as algorithm-based fault tolerance (ABFT). Banerjee and Abraham have shown that an ABFT scheme can be modeled as a tripartite graph consisting of processors (P), data (D), and checks (C). Any technique for designing ABFT systems requires a procedure for synthesizing a DC relationship, which not only has a low overhead but also has all the properties required by the designer. The main contribution of this work is to propose a simple and novel algorithm called RANDGEN to generate DC graphs. This synthesis approach itself is very fast and can be fully parallelized. By simply varying its parameters, the same algorithm RANDGEN can produce DC graphs with a wide spectrum of properties, many of which have been considered very important in recent ABFT designs. RANDGEN produces s-error-detectable DC graphs with asymptotically the least number of checks for the first time. RANDGEN can also produce s-error-locatable DC graphs using only a small number of checks. This is the first general procedure for producing error-locatable graphs for any value of s. Another important outstanding problem in DC graph design is providing fast and practical methods for actually locating the errors in the data from the output pattern at the checks. We show that RANDGEN can be used to design DC graphs, which permit easy diagnosis, again with a small number of checks. It has been pointed out previously that ''uniform'' checks may simplify the design of the ABFT system. We show how RANDGEN can be modified very simply to produce uniform s-error-detectable/locatable DC graphs. Finally, we show how one can generalize these results to synthesize strictly s-error-detectable/locatable DC graphs which ca

关键词： algorithm-based fault tolerance CHECKSUM ENCODING CONCURRENT ERROR DETECTION CONCURRENT ERROR LOCATION MAJORITY DIAGNOSIS RANDOMIZED algorithmS UNIFORM CHECKS

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An algorithm-based error detection scheme for the multigrid method

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IEEE TRANSACTIONS ON COMPUTERS 2003年第9期52卷 1089-1099页

作者： Mishra, A Banerjee, P Virginia Polytech Inst & State Univ Bradley Dept Elect & Comp Engn Blacksburg VA 24061 USA Northwestern Univ Dept Elect & Comp Engn Ctr Parallel & Distributed Comp Evanston IL 60208 USA

algorithm-based fault tolerance (ABFT) is a technique to provide system level error detection and correction on array processors as well as multiprocessors at a low cost. Since the early 80s the technique has been extensively applied to several linear algebraic algorithms, e.g., matrix multiplication, Gaussian elimination, QR factorization, and singular value decompositions, etc. An important class of problems in numerical linear algebra dealing with the iterative solution of linear algebraic equations arising due to the finite difference discretization or the finite element discretization of a partial differential equation, however, has been overlooked. The only exception is the recent application of algorithm based error detection (ABED) encodings to the successive overrelaxation algorithm for Laplace's equation [11]. In this paper, ABED is applied to a multigrid algorithm for the iterative solution of a Poisson equation in two dimensions. Invariants are created to implement checking in the relaxation, the restriction, and the interpolation operators. Modifications to invariants due to roundoff errors accumulated within the operators, which often lead to a situation known as false alarms, have been addressed by deriving the expressions for the roundoff errors in the algebraic processes in the operators and correcting the invariants accordingly, ABED encoded multigrid algorithm is shown to be insensitive to the size and the range of the input data besides providing excellent error coverage at a low latency for floating-point, integer, and memory errors.

关键词： algorithm-based fault tolerance multigrid method rounding error analysis parallel error detection partial differential equations

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A WELL CONDITIONED CHECKSUM SCHEME FOR algorithmIC fault tolerance

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INTEGRATION-THE VLSI JOURNAL 1991年第1期12卷 21-32页

作者： BOLEY, DL LUK, FT CORNELL UNIV SCH ELECT ENGN ITHACA NY 14853 USA

The weighted checksum scheme has been proposed as a low-cost fault tolerant procedure for parallel matrix computations. To guarantee multiple error detection and correction, the chosen weight vectors must satisfy some very specific properties about linear independence. However, previous weight generating methods that fulfill the independence criteria have troubles with numerical overflow. We will present a new scheme that generates weight vectors via Chebyshev polynomials to meet the requirements about independence and to avoid the difficulties with overflow.

关键词： algorithm-based fault tolerance CHEBYSHEV POLYNOMIALS LANCZOS algorithm BERLEKAMP-MASSEY algorithm

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fault-tolerant QRD recursive least squares

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IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES 1996年第2期143卷 137-144页

作者： Connolly, MP Fitzpatrick, P National Microelectronics Research Centre Cork Ireland

The authors present an algorithm-based fault tolerant scheme for recursive least squares, appropriate for applications in adaptive signal processing. The technique is closely focused on the Gentleman-Kung-McWhirter triangular systolic array architecture for QR decomposition. Assuming that the array is subject to transient faults, widely separated in time and each affecting a single processor, an algorithm is given that corrects the full triangular array with computational overhead equivalent, on average, to the interpolation of a single extra vector into the data stream. No output residuals are lost in the fault recovery. The analysis is extended to a fault-tolerant algorithm for linearly constrained QR decomposition.

关键词： algorithm-based fault tolerance error correction QR decomposition adaptive filtering linearly constrained QRD

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fault tolerance design in JPEG 2000 image compression system

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IEEE TRANSACTIONS ON DEPENDABLE AND SECURE COMPUTING 2005年第1期2卷 57-75页

作者： Nguyen, C Redinbo, GR Univ Calif Davis Dept Elect & Comp Engn Davis CA 95616 USA

The JPEG 2000 image compression standard is designed for a broad range of data compression applications. The new standard is based on wavelet technology and layered coding in order to provide a rich feature compressed image stream. The implementations of the JPEG 2000 codec are susceptible to computer-induced soft errors. One situation requiring fault tolerance is remote-sensing satellites, where high energy, particles and radiation produce single event upsets corrupting the highly susceptible data compression operations. This paper develops fault tolerance error-detecting capabilities for the major subsysyems that constitute a JPEG 2000 standard. The nature of the subsystem dictates the realistic fault model where some parts have numerical error impacts whereas others are properly modeled using bit-level variables. The critical operations of subunits such as Discrete Wavelet Transform (DWT) and quantization are protected against numerical errors. Concurrent error detection techniques are applied to accommodate the data type and numerical operations in each processing unit. On the other hand, the Embedded Block Coding with Optimal Truncation (EBCOT) system and the bitstream formation unit are protected against soft-error effects using binary decision variables and cyclic redundancy check (CRC) parity values, respectively. The techniques achieve excellent error-detecting capability at only a slight increase in complexity. The design strategies have been tested using Matlab programs and simulation results are presented.

关键词： fault-tolerant source coding soft errors JPEG 2000 standard data compression Discrete Wavelet Transform (DWT) algorithm-based fault tolerance error control codes Huffman coding error-checking concurrent error detection hardware reliability weighted sum parity

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Low-Cost Online Convolution Checksum Checker

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2022年第2期30卷 201-212页

作者： Filippas, Dionysios Margomenos, Nikolaos Mitianoudis, Nikolaos Nicopoulos, Chrysostomos Dimitrakopoulos, Giorgos Democritus Univ Thrace Dept Elect & Comp Engn Xanthi 67100 Greece Univ Cyprus Dept Elect & Comp Engn CY-1678 Nicosia Cyprus

Managing random hardware faults requires the faults to be detected online, thus simplifying recovery. algorithm-based fault tolerance has been proposed as a low-cost mechanism to check online the result of computations against random hardware failures. In this case, the checksum of the actual result is checked against a predicted checksum computed in parallel by a hardware checker. In this work, we target the design of such checkers for convolution engines that are currently the most critical building block in image processing and computer vision applications. The proposed convolution checksum checker, named ConvGuard, utilizes a newly introduced invariance condition of convolution to predict implicitly the output checksum using only the pixels at the border of the input image. In this way, ConvGuard reduces the power required for accumulating the input pixels without requiring large buffers to hold intermediate checksum results. The design of ConvGuard is generic and can be configured for different output sizes and strides. The experimental results show that ConvGuard utilizes only a small percentage of the area/power of an efficient convolution engine while being significantly smaller and more power efficient than a state-of-the-art checksum checker for various practical cases.

关键词： Convolution Hardware Engines Computer architecture fault tolerant systems fault tolerance Convolutional neural networks algorithm-based fault tolerance convolution error detection reliability

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Failure-detecting arithmetic convolutional codes and an iterative correcting strategy

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IEEE TRANSACTIONS ON COMPUTERS 2003年第11期52卷 1434-1442页

作者： Redinbo, GR Univ Calif Davis Dept Elect & Comp Engn Davis CA 95616 USA

Errors due to failures in data processing algorithms may be detected and even corrected by employing systematic convolutional codes defined over the fixed-point arithmetic structures supporting the computations. A new class of arithmetic convolutional codes using symbols from the finite ring associated with normal signed arithmetic is based on binary burst-correcting codes and a code's performance in the larger context exceeds that of an underlying basis code. When failures satisfy the usual guard band requirements for the binary code, error correction is possible using an iterative feedback decoder processing syndromes that are defined over the integers modulo a power of two. A class of high rate burst-correcting codes is discussed in more detail and their properties guarantee the detection of the onset of errors. The corrector also contains failure error-detecting capabilities.

关键词： algorithm-based fault tolerance convolutional codes over integers iterative decoding free modules fixed-point arithmetic burst-correcting codes syndrome decoding real number codes

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Concurrent error detection in wavelet lifting transforms

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IEEE TRANSACTIONS ON COMPUTERS 2004年第10期53卷 1291-1302页

作者： Redinbo, GR Nguyen, C Univ Calif Davis Dept Elect & Comp Engn Livermore CA 95616 USA

Wavelet transforms, central to multiresolution signal analysis and important in the JPEG2000 image compression standard, are quite susceptible to computer-induced errors because of their pipelined structure and multirate processing requirements. Such errors emanate from computer hardware, software bugs, or radiation effects from the surrounding environment. Implementations use lifting schemes, which employ update and prediction estimation stages, and can spread a single numerical error caused by failures to many output transform coefficients without any features to warn data users. This paper proposes an efficient method to detect the arithmetic errors using weighted sums of the wavelet coefficients at the output compared with an equivalent parity value derived from the input data. Two parity values may straddle a complete multistage transform or several values may be used, each pair covering a single stage. There is greater error-detecting capability at only a slight increase in complexity when parity pairs are interspersed between stages. With the parity weighting design scheme, a single error introduced at a lifting section can be detected. The parity computation operation is properly viewed as an inner product between weighting values and the data, motivating the use of dual space functionals related to the error gain matrices. The parity weighting values are generated by a combination of dual space functionals. An iterative procedure for evaluating the design of the parity weights has been incorporated in Matlab code and simulation results are presented.

关键词： wavelet transforms concurrent error detection weighted sum parity real number codes algorithm-based fault tolerance error gain matrices dual space functionals biorthogonality

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