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检索条件"主题词=algorithm-based fault tolerance"

共 79 条记录，以下是61-70 订阅

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Protecting wavelet lifting transforms

Protecting wavelet lifting transforms

引用

10th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2004)

作者： Redinbo, GR Nguyen, C Univ Calif Davis Dept Elect & Comp Engn Davis CA 95616 USA

ISBN: (纸本)0769520766

Wavelet transforms are the central to many applications in image processing and data compression. They have banks of multi-rate filters that are difficult to protect from. computer-induced numerical errors. An efficient algorithm-based fault tolerance approach is proposed for detecting arithmetic errors in the output data. Concurrent weighted parity values are designed to detect the effects of a single numerical error within the transform structure. The parity calculations use weighted sums of data, where the input parity weighting is related to the weighting used on the output data. Each parity computation is properly viewed as an inner product between weighting values and the data motivating the use of dual space functionals related to the error gain matrices that describe error propagations to the output. The parity weighting values are defined by a combination of dual space functionals. An iterative procedure for evaluating the design of the parity weights has been incorporated in Matlab code.

关键词： wavelet transforms concurrent error detection weighted sum parity real number codes algorithm-based fault tolerance error gain matrices dual space functionals bi-orthogonality

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A Highly-Efficient Error Detection Technique for General Matrix Multiplication using Tiled Processing on SIMD Architecture 40

A Highly-Efficient Error Detection Technique for General Mat...

引用

IEEE 40th International Conference on Computer Design (ICCD)

作者： Mummidi, Chandra Sekhar Bal, Sandeep Goldstein, Brunno F. Srinivasan, Sudarshan Kundu, Sandip Univ Massachusetts Amherst MA 01003 USA Univ Fed Rio de Janeiro UFRJ Rio De Janeiro Brazil Intel Labs Mumbai Maharashtra India

ISBN: (数字)9781665461863

ISBN: (纸本)9781665461863

General Matrix Multiplication (GEMM) is instrumental in myriads of scientific, high-performance computing, and machine learning applications such as computer vision, recommendation models, and weather forecasts. It is vital to make them fail-safe in safety-critical and high-precision applications. Companies like Meta and Google have recently reported sporadic silent errors in GEMM computations traced to hardware sources. Silent errors are hard to detect, requiring specialized solutions to detect them. Hardware redundancy approaches such as double or triple modular redundancy effectively detect or correct such errors, but they have a large area and power overhead. algorithm-based fault tolerance (ABFT) has been shown to offer an effective alternative at a far lower overhead. Modern CPUs feature advanced vector extensions (AVX) capable of executing SIMD instructions. This paper describes a new ABFT approach designed to take advantage of the AVX feature. Our core algorithm relies on the classical tile-based outer-product approach but enhances standard check-sum calculation using a tile vector. The implementation parameters are fine-tuned to fit the available number of AVX registers. Our results indicate that we can achieve 100% error detection in GEMM at an overhead of just 0.21% for the integer data type. Unfortunately, due to rounding errors, addition of floating-point numbers is not an associative operation, creating difficulties for ABFT. To mitigate the impact of rounding errors, we introduce the concept of relative error checking and perform error analysis for various error classes to show that the proposed approach totally eliminates false positive errors.

关键词： algorithm-based fault tolerance Tile-based checksum Matrix Multiplication Rounding Error Estimation

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Highly Scalable algorithms for the Sparse Grid Combination Technique 29

Highly Scalable Algorithms for the Sparse Grid Combination T...

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29th IEEE International Parallel and Distributed Processing Symposium (IPDPS)

作者： Strazdins, Peter E. Ali, Md Mohsin Harding, Brendan Australian Natl Univ Res Sch Comp Sci Canberra ACT Australia Australian Natl Univ Inst Math Sci Canberra ACT Australia

ISBN: (纸本)9781467376846

Many petascale and exascale scientific simulations involve the time evolution of systems modelled as Partial Differential Equations (PDEs). The sparse grid combination technique (SGCT) is a cost-effective method for solve time-evolving PDEs, especially for higher-dimensional problems. It consists of evolving PDE over a set of grids of differing resolution in each dimension, and then combining the results to approximate the solution of the PDE on a grid of high resolution in all dimensions. It can also be extended to support algorithmic-based fault-tolerance, which is also important for computations at this scale. In this paper, we present two new parallel algorithms for the SGCT that supports the full distributed memory parallelization over the dimensions of the component grids, as well as over the grids as well. The direct algorithm is so called because it directly implements a SGCT combination formula. The second algorithm converts each component grid into their hierarchical surpluses, and then uses the direct algorithm on each of the hierarchical surpluses. The conversion to/from the hierarchical surpluses is also an important algorithm in its own right. An analysis of both indicates the direct algorithm minimizes the number of messages, whereas the hierarchical surplus minimizes memory consumption and offers a reduction in bandwidth by a factor of 1-2-d, where d is the dimensionality of the SGCT. However, this is offset by its incomplete parallelism and factor of two load imbalance in practical scenarios. Our analysis also indicates both are suitable in a bandwidth-limiting regime. Experimental results including the strong and weak scalability of the algorithms indicates that, for scenarios of practical interest, both are sufficiently scalable to support large-scale SGCT but the direct algorithm has generally better performance, to within a factor of 2. Hierarchical surplus formation is much less communication intensive, but shows less scalability with increasin

关键词： high performance computing parallel computing PDE solvers sparse grid combination technique algorithm-based fault tolerance

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ERROR DETECTION IN DIGITAL NEURAL NETWORKS - AN algorithm-based APPROACH FOR INNER PRODUCT PROTECTION

ERROR DETECTION IN DIGITAL NEURAL NETWORKS - AN ALGORITHM-BA...

引用

5th SPIE Conference on Advanced Signal Processing - algorithms, Architectures, and Implementations

作者： BREVEGLIERI, L PIURI, V POLITECN MILAN DEPT ELECTR & INFORMATI-20133 MILANITALY

ISBN: (纸本)0819416207

Artificial Neural Networks are an interesting solution for several real-time applications in the area of signal and image processing, in particular since recent advances in VLSI integration technologies allow for efficient hardware realizations. The use of dedicated circuits implementing the neural networks in mission-critical applications requires a high level of protection with respect to errors due to faults to guarantee output credibility and system availability. In this paper, the problem of concurrent error detection in dedicated neural networks is discussed by adopting an algorithm-based approach to check the inner product, i.e., the most of the computation performed in the neural network. Effectiveness and efficiency of this technique is shown and evaluated for the widely-used classes of neural paradigms.

关键词： DIGITAL NEURAL NETWORKS CONCURRENT ERROR DETECTION algorithm-based fault tolerance

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3D Coded SUMMA: Communication-Efficient and Robust Parallel Matrix Multiplication 26th

3D Coded SUMMA: Communication-Efficient and Robust Parallel ...

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26th International Conference on Parallel and Distributed Computing (Euro-Par)

作者： Jeong, Haewon Yang, Yaoqing Gupta, Vipul Engelmann, Christian Low, Tze Meng Cadambe, Viveck Ramchandran, Kannan Grover, Pulkit Carnegie Mellon Univ Pittsburgh PA 15213 USA Univ Calif Berkeley Berkeley CA USA Oak Ridge Natl Lab Oak Ridge TN USA Penn State Univ State Coll PA USA

ISBN: (纸本)9783030576752;9783030576745

In this paper, we propose a novel fault-tolerant parallel matrix multiplication algorithm called 3D Coded SUMMA that achieves higher failure-tolerance than replication-based schemes for the same amount of redundancy. This work bridges the gap between recent developments in coded computing and fault-tolerance in high-performance computing (HPC). The core idea of coded computing is the same as algorithm-based fault-tolerance (ABFT), which is weaving redundancy in the computation using error-correcting codes. In particular, we show that MatDot codes, an innovative code construction for parallel matrix multiplications, can be integrated into three-dimensional SUMMA (Scalable Universal Matrix Multiplication algorithm [30]) in a communication-avoiding manner. To tolerate any two node failures, the proposed 3D Coded SUMMA requires similar to 50% less redundancy than replication, while the overhead in execution time is only about 5-10%.

关键词： Parallel matrix multiplication fault-tolerant algorithms algorithm-based fault tolerance Coded computing Communication-efficient algorithms Error detection and correction

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Combining backward and forward recovery to cope with silent errors in iterative solvers 29

Combining backward and forward recovery to cope with silent ...

引用

29th IEEE International Parallel and Distributed Processing Symposium (IPDPS)

作者： Fasi, Massimiliano Robert, Yves Ucar, Bora Ecole Normale Super Lyon Lyon France CNRS F-75700 Paris France INRIA Rocquencourt France Univ Bologna I-40126 Bologna Italy Univ Knoxville Knoxville TN USA

ISBN: (纸本)9781467376846

Several recent papers have introduced a periodic verification mechanism to detect silent errors in iterative solvers. Chen [PPoPP' 13, pp. 167-176] has shown how to combine such a verification mechanism (a stability test checking the orthogonality of two vectors and recomputing the residual) with checkpointing: the idea is to verify every d iterations, and to checkpoint every c x d iterations. When a silent error is detected by the verification mechanism, one can rollback to, and re-execute from, the last checkpoint. In this paper, we also propose to combine checkpointing and verification, but we use ABFT rather than stability tests. ABFT can be used for error detection, but also for error detection and correction, allowing a forward recovery (and no rollback nor re-execution) when a single error is detected. We introduce an abstract performance model to compute the performance of all schemes, and we instantiate it using the Conjugate Gradient algorithm. Finally, we validate our new approach through a set of simulations.

关键词： fault-tolerance Silent errors algorithm-based fault tolerance Checkpointing Sparse matrix-vector multiplication Performance model

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Supporting the Development of Resilient Message Passing Applications using Simulation

Supporting the Development of Resilient Message Passing Appl...

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22nd Euromicro International Conference on Parallel, Distributed, and Network-based Processing (PDP)

作者： Naughton, Thomas Engelmann, Christian Vallee, Geoffroy Boehm, Swen Oak Ridge Natl Lab Comp Sci & Math Div Oak Ridge TN 37831 USA

ISBN: (纸本)9781479927289

An emerging aspect of high-performance computing (HPC) hardware/software co-design is investigating performance under failure. The work in this paper extends the Extreme-scale Simulator (xSim), which was designed for evaluating the performance of message passing interface (MPI) applications on future HPC architectures, with fault-tolerant MPI extensions proposed by the MPI fault tolerance Working Group. xSim permits running MPI applications with millions of concurrent MPI ranks, while observing application performance in a simulated extreme-scale system using a lightweight parallel discrete event simulation. The newly added features offer user-level failure mitigation (ULFM) extensions at the simulated MPI layer to support algorithm-based fault tolerance (ABFT). The presented solution permits investigating performance under failure and failure handling of ABFT solutions. The newly enhanced xSim is the very first performance tool that supports ULFM and ABFT.

关键词： High-performance Computing Message Passing Interface algorithm-based fault tolerance Parallel Discrete Event Simulation Performance Prediction

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In-Situ Mitigation of Silent Data Corruption in PDE Solvers

In-Situ Mitigation of Silent Data Corruption in PDE Solvers

引用

ACM Workshop on fault-tolerance for HPC at Extreme Scale (FTXS)

作者： Salloum, Maher Mayo, Jackson R. Armstrong, Robert C. Sandia Natl Labs Livermore CA 94551 USA

ISBN: (纸本)9781450343497

We present algorithmic techniques for parallel PDE solvers that leverage numerical smoothness properties of physics simulation to detect and correct silent data corruption within local computations. We initially model such silent hardware errors (which are of concern for extreme scale) via injected DRAM bit flips. Our mitigation approach generalizes previously developed "robust stencils" and uses modified linear algebra operations that spatially interpolate to replace large outlier values. Prototype implementations for 1D hyperbolic and 3D elliptic solvers, tested on up to 2048 cores, show that this error mitigation enables tolerating orders of magnitude higher bit-flip rates. The runtime overhead of the approach generally decreases with greater solver scale and complexity, becoming no more than a few percent in some cases. A key advantage is that silent data corruption can be handled transparently with data in cache, reducing the cost of false-positive detections compared to rollback approaches.

关键词： Silent data corruption resilience algorithm-based fault tolerance partial differential equation numerical methods

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A Case Study of Designing Efficient algorithm-based fault Tolerant Application for Exascale Parallelism

A Case Study of Designing Efficient Algorithm-based Fault To...

引用

26th IEEE International Parallel and Distributed Processing Symposium (IPDPS) / Workshop on High Performance Data Intensive Computing

作者： Yao, Erlin Wang, Rui Chen, Mingyu Tan, Guangming Sun, Ninghui Chinese Acad Sci Inst Comp Technol State Key Lab Comp Architecture Beijing Peoples R China

ISBN: (纸本)9780769546759

fault tolerance overhead of high performance computing (HPC) applications is becoming critical to the efficient utilization of HPC systems at large scale. Today's HPC applications typically tolerate fail-stop failures by checkpointing. However, checkpointing will lose its efficiency when system becoming very large. An alternative method is algorithm-based fault recovery which has been proved to be more efficient than checkpointing. In this paper, we first point out by theoretical analysis that algorithm-based fault recovery will also lose its efficiency when systems scale up to Exaflops. Then, a more efficient algorithm-based fault tolerance scheme for HPC applications at large scale is presented. The new method has two novel skills. One is algorithm-based hot replacement, which avoids the stop-and-wait time after failure. Second is background accelerated recovery, which guarantees the system to endure multiple failures in succession. As a case study, this method is incorporated to High Performance Linpack (HPL). Theoretical analysis shows that the fault tolerance overhead can be reduced to 2/log(2)(p) of that of algorithm-based fault recovery method (p is the number of computation processes), so that the new method will still be efficient in Exascale. Experimental results for up to 1800 processes show that the overhead of the new method is about 25% of that of algorithm-based fault recovery method, which is close to the theoretical prediction.

关键词： Exascale algorithm-based fault tolerance High Performance Linpack

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Concurrent error detection in fast unitary transform algorithms

Concurrent error detection in fast unitary transform algorit...

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International Conference on Dependable Systems and Networks (DSN 2001)

作者： Redinbo, GR Univ Calif Davis Dept Elect & Comp Engn Davis CA 95616 USA

ISBN: (纸本)0769511023

Discrete fast unitary transform algorithms, of which the fast Fourier transform (FFT) and fast discrete Cosine transform (DCT) are practical examples, are highly susceptible to temporary calculation failures because of their interconnected computational flows. Many error detection techniques for FFT algorithms have been reported, but fault tolerance issues for other important transforms have not been addressed as vigorously. A general design and analysis approach for all fast unitary transforms is presented. It relies on fundamental linear algebra methods coupled with associated dual space representations that are natural descriptions of real parity values. Basic output error patterns from single computational errors are used to define an equal-sized group of dual space basis vectors on which practical parity weighting functions maybe evaluated. An iterative design approach leads to complete single error detection capabilities. FFT and fast DCT examples are given.

关键词： algorithm-based fault tolerance numerical error detection real number parity values fast Fourier transform fast discrete cosine transform

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