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检索条件"主题词=algorithm-circuit codesign"
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A Communication-Aware DNN Accelerator on ImageNet Using In-Memory Entry-Counting Based algorithm-circuit-Architecture Co-Design in 65-nm CMOS
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IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN circuitS AND SYSTEMS 2020年 第3期10卷 283-294页
作者: Zhu, Haozhe Chen, Chixiao Liu, Shiwei Zou, Qiaosha Wang, Mingyu Zhang, Lihua Zeng, Xiaoyang Richard Shi, C. -J. Fudan Univ State Key Lab ASIC & Syst Shanghai 201203 Peoples R China Fudan Univ Shanghai Engn Res Ctr AI & Robot Shanghai 200433 Peoples R China Fudan Univ Inst Brain Inspired Circuits & Syst Shanghai 201203 Peoples R China Univ Washington Dept Elect & Comp Engn Seattle WA 98195 USA
This article presents a communication-aware processing-in-memory deep neural network accelerator, which implements an in-memory entry-counting scheme for low bit-width quantized multiplication-and-accumulations (MACs)... 详细信息
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