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检索条件"主题词=algorithm-hardware co-design"

共 36 条记录，以下是21-30 订阅

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EIE: Efficient Inference Engine on compressed Deep Neural Network 16

EIE: Efficient Inference Engine on Compressed Deep Neural Ne...

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43rd ACM/IEEE Annual International Symposium on computer Architecture (ISCA)

作者： Han, Song Liu, Xingyu Mao, Huizi Pu, Jing Pedram, Ardavan Horowitz, Mark A. Dally, William J. Stanford Univ Stanford CA 94305 USA NVIDIA Santa Clara CA USA

ISBN: (纸本)9781467389471

State-of-the-art deep neural networks (DNNs) have hundreds of millions of connections and are both computationally and memory intensive, making them difficult to deploy on embedded systems with limited hardware resources and power budgets. While custom hardware helps the computation, fetching weights from DRAM is two orders of magnitude more expensive than ALU operations, and dominates the required power. Previously proposed 'Deep compression' makes it possible to fit large DNNs (AlexNet and VGGNet) fully in on-chip SRAM. This compression is achieved by pruning the redundant connections and having multiple connections share the same weight. We propose an energy efficient inference engine (EIE) that performs inference on this compressed network model and accelerates the resulting sparse matrix-vector multiplication with weight sharing. Going from DRAM to SRAM gives EIE 120x energy saving;Exploiting sparsity saves 10x;Weight sharing gives 8x;Skipping zero activations from ReLU saves another 3x. Evaluated on nine DNN benchmarks, EIE is 189x and 13x faster when compared to CPU and GPU implementations of the same DNN without compression. EIE has a processing power of 102 GOPS working directly on a compressed network, corresponding to 3 TOPS on an uncompressed network, and processes FC layers of AlexNet at 1.88x10(4) frames/sec with a power dissipation of only 600mW. It is 24,000x and 3,400x more energy efficient than a CPU and GPU respectively. compared with DaDianNao, EIE has 2.9x, 19x and 3x better throughput, energy efficiency and area efficiency.

关键词： Deep Learning Model compression hardware Acceleration algorithm-hardware co-design ASIC

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Unearthing the Potential of Spiking Neural Networks

Unearthing the Potential of Spiking Neural Networks

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27th design, Automation and Test in Europe conference and Exhibition (DATE)

作者： Chowdhury, Sayced Shafayet Kosta, Adarsh Kumar Sharma, Dccpika Apolinario, Marco P. E. Roy, Kaushik Purdue Univ Sch ECE W Lafayette IN 47907 USA

ISBN: (纸本)9798350348606;9783981926385

Spiking neural networks (SNNs) offer a promising alternative to traditional analog neural networks (ANNs), especially for sequential tasks, with enhanced energy efficiency. The internal memory in SNNs obtained through the membrane potential equips them with innate lightweight temporal processing capabilities. However, the unique advantages of this temporal dimension of SNNs have not yet been effectively harnessed. To that end, this article delves deeper into the what, why and where of SNNs. By considering event-based optical flow as an exemplary task in vision-based navigation, we highlight that the true potential of SNNs lies in sequential tasks. The event-driven recurrent dynamics of a spiking neuron merged harmoniously with event camera inputs enables SNNs to outperform corresponding ANNs with a lower number of parameters for optical flow. Furthermore, we demonstrate that SNNs can be synergistically combined with ANNs to form SNN-ANN hybrids to obtain the best of both worlds in terms of accuracy, energy, memory, and training efficiency. Additionally, the emergence of various near-memory and in-memory computing techniques has propelled efficient implementation of these approaches. Overall, the immediate future of SNNs looks exciting, as we discover the niche of SNNs, comprising sequential tasks with low power requirements.

关键词： SNNs SNN-ANN Hybrids Sequential Tasks Neuromorphic hardware algorithm-hardware co-design

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An Efficient and Low-Power MLP Accelerator Architecture Supporting Structured Pruning, Sparse Activations and Asymmetric Quantization for Edge computing 3

An Efficient and Low-Power MLP Accelerator Architecture Supp...

引用

IEEE 3rd International conference on Artificial Intelligence Circuits and Systems (AICAS)

作者： Lin, Wei-Chen Chang, Ya-Chu Huang, Juinn-Dar Natl Yang Ming Chiao Tung Univ Inst Elect Hsinchu Taiwan

ISBN: (纸本)9781665419130

Multilayer perceptron (MLP) is one of the most popular neural network architectures used for classification, regression, and recommendation systems today. In this paper, we propose an efficient and low-power MLP accelerator for edge computing. The accelerator has three key features. First, it aligns with a novel structured weight pruning algorithm that merely needs minimal hardware support. Second, it takes advantage of activation sparsity for power minimization. Third, it supports asymmetric quantization on both weights and activations to boost the model accuracy especially when those values are in low-precision formats. Furthermore, the number of PEs is determined based on the available external memory bandwidth to ensure the high PE utilization, which avoids area and energy wastes. Experiment results show that the proposed MLP accelerator with only 8 MACs operates at 1.6GHz using the TSMC 40nm technology, delivers 899GOPS equivalent computing power after structured weight pruning on a well-known image classification model, and achieves an equivalent energy efficiency of 9.7TOPS/W, while the model accuracy loss is less than 0.3% with the help of asymmetric quantization.

关键词： multilayer perceptron model compression hardware accelerator algorithm-hardware co-design

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FACT: FFN-Attention co-optimized Transformer Architecture with Eager correlation Prediction 23

FACT: FFN-Attention Co-optimized Transformer Architecture wi...

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50th Annual International Symposium on computer Architecture (ISCA)

作者： Qin, Yubin Wang, Yang Deng, Dazheng Zhao, Zhiren Yang, Xiaolong Liu, Leibo Wei, Shaojun Hu, Yang Yin, Shouyi Tsinghua Univ Beijing Peoples R China

ISBN: (纸本)9798400700958

Transformer model is becoming prevalent in various AI applications with its outstanding performance. However, the high cost of computation and memory footprint make its inference inefficient. We discover that among the three main computation modules in a Transformer model (QKV generation, attention computation, FFN), it is the QKV generation and FFN that contribute to the most power cost. While the attention computation, focused by most previous works, only has decent power share when dealing with extremely long inputs. Therefore, in this paper, we propose FACT, an efficient algorithm-hardware co-design optimizing all three modules of Transformer. We first propose an eager prediction algorithm which predicts the attention matrix before QKV generation. It further detects the unnecessary computation in QKV generation and assigns mixed-precision FFN with the predicted attention, which helps improve the throughput. Further, we propose FACT accelerator to efficiently support eager prediction with three designs. It avoids the large overhead of prediction by using log-based add-only operations for prediction. It eliminates the latency of prediction through an out-of-order scheduler that makes the eager prediction and computation work in full pipeline. It additionally avoids memory access conflict in the mixed-precision FFN with a novel diagonal storage pattern. Experiments on 22 benchmarks show that our FACT improves the throughput of the whole Transformer by 3.59x on the geomean average. It achieves an enviable 47.64x and 278.1x energy saving when computing attention, compared to previous attention-optimization-only SOTA works ELSA and Sanger. Further, FACT achieves an energy efficiency of 4388 GOPS/W performing the whole Transformer layer on average, which is 94.98x higher than Nvidia V100 GPU.

关键词： transformer hardware accelerator efficient computing algorithm-hardware co-design neural network

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Recompiling QAOA Circuits on Various Rotational Directions 24

Recompiling QAOA Circuits on Various Rotational Directions

引用

International conference on Parallel Architectures and compilation Techniques (PACT)

作者： Jang, Enhyeok Ha, Dongho Choi, Seungwoo Kim, Youngmin Kwon, Jaewon Lee, Yongju Ahn, Sungwoo Kim, Hyungseok Ro, Won Woo Yonsei Univ Seoul South Korea

ISBN: (数字)9798400706318

ISBN: (纸本)9798400706318

The quantum approximate optimization algorithm (QAOA) is introduced to efficiently solve combinatorial optimization problems. Despite the promise of QAOA, the cost of executing QAOA circuits at scale for quantum advantage may still be excessive for the near-future quantum device. We observe the increasing overhead of QAOA circuit execution in the native gate translation. To execute QAOA circuits on a real quantum computing device, Hamiltonians composed of predefined specific rotations (e.g., ZZ and X) should be decomposed into finite native gates. By adopting rotational combinations that utilize native gates more directly than the standard QAOA circuit model, the execution cost on real quantum devices can be reduced. In this study, we propose Racoon (Rotational Space Virtualization for QAOA Ansatz), an algorithm-hardware co-design approach that revisits the synthesis conditions of QAOA circuits and selects alternative candidates with different rotational combinations. Our analysis of six commercial quantum processors demonstrates that applying Racoon to QAOA circuits for the 4-node Sherrington-Kirkpatrick model reduces the number of native gates by an average of 23% and up to 79%. consequently, using Racoon results in 43% fewer training epochs, 41% lower training energy consumption, and a 6% improvement in inference on average compared to standard QAOA. Racoon consistently reduces circuit depth as the number of qubits and layers increases, achieving 123x more circuit depth reduction compared to the recently proposed Depth First Search (DFS)-based method. Furthermore, we confirm that Racoon's method can be extended to State-of-The-Art QAOAs with modified ansatze and to the variational quantum eigensolver (VQE).

关键词： Native Gate Quantum compiler algorithm-hardware co-design

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Efficient Network construction Through Structural Plasticity

Efficient Network Construction Through Structural Plasticity

引用

1st AI compute Symposium (AICS)

作者： Du, Xiaocong Li, Zheng Ma, Yufei Cao, Yu Arizona State Univ Sch Elect Comp & Energy Engn Tempe AZ 85287 USA Arizona State Univ Sch Comp Informat & Decis Syst Engn Tempe AZ 85287 USA

Deep Neural Networks (DNNs) on hardware is facing excessive computation cost due to the massive number of parameters. A typical training pipeline to mitigate over-parameterization is to pre-define a DNN structure with redundant learning units (filters and neurons) with the goal of high accuracy, then to prune redundant learning units after training with the purpose of efficient inference. We argue that it is sub-optimal to introduce redundancy into training in order to reduce redundancy later in inference. Moreover, the fixed network structure further results in poor adaption to dynamic tasks, such as lifelong learning. In contrast, structural plasticity plays an indispensable role in mammalian brains to achieve compact and accurate learning. Throughout the lifetime, active connections are continuously created while those that are no longer important are degenerated. Inspired by such observation, we propose a training scheme, namely continuous Growth and Pruning (CGaP), where we start the training from a small network seed, then literally execute continuous growth by adding important learning units and finally prune secondary ones for efficient inference. The inference model generated from CGaP is sparse in the structure, largely decreasing the inference power and latency when deployed on hardware platforms. With popular DNN structures on representative datasets, the efficacy of CGaP is benchmarked by both algorithmic simulation and architectural modeling on Field-programmable Gate Arrays (FPGA). For example, CGaP decreases the FLOPs, model size, DRAM access energy and inference latency by 63.3%, 64.0%, 11.8% and 40.2%, respectively, for ResNet-110 on CIFAR-10.

关键词： Deep learning structural plasticity model pruning hardware acceleration algorithm-hardware co-design

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DUAL: Acceleration of Clustering algorithms using Digital-based Processing In-Memory 53

DUAL: Acceleration of Clustering Algorithms using Digital-ba...

引用

53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： Imani, Mohsen Pampana, Saikishan Gupta, Saransh Zhou, Minxuan Kim, Yeseong Rosing, Tajana UC Irvine Dept Comp Sci Irvine CA 92697 USA DGIST Dept Informat & Commun Engn Daegu South Korea Univ Calif San Diego Dept Comp Sci & Engn San Diego CA USA

ISBN: (数字)9781728173832

ISBN: (纸本)9781728173832

Today's applications generate a large amount of data that need to be processed by learning algorithms. In practice, the majority of the data are not associated with any labels. Unsupervised learning, i.e., clustering methods, are the most commonly used algorithms for data analysis. However, running clustering algorithms on traditional cores results in high energy consumption and slow processing speed due to a large amount of data movement between memory and processing units. In this paper, we propose DUAL, a Digital-based Unsupervised learning AcceLeration, which supports a wide range of popular algorithms on conventional crossbar memory. Instead of working with the original data, DUAL maps all data points into high-dimensional space, replacing complex clustering operations with memory-friendly operations. We accordingly design a PIM-based architecture that supports all essential operations in a highly parallel and scalable way. DUAL supports a wide range of essential operations and enables in-place computations, allowing data points to remain in memory. We have evaluated DUAL on several popular clustering algorithms for a wide range of large-scale datasets. Our evaluation shows that DUAL provides a comparable quality to existing clustering algorithms while using a binary representation and a simplified distance metric. DUAL also provides 58.8x speedup and 251.2x energy efficiency improvement as compared to the state-of-the-art solution running on GPU.

关键词： Processing in-memory Unsupervised learning Hyperdimensional computing algorithm-hardware co-design

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EyecoD: Eye Tracking System Acceleration via FlatCam-based algorithm & Accelerator co-design 22

EyeCoD: Eye Tracking System Acceleration via FlatCam-based A...

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49th IEEE/ACM Annual International Symposium on computer Architecture (ISCA)

作者： You, Haoran Wan, Cheng Zhao, Yang Yu, Zhongzhi Fu, Yonggan Yuan, Jiayi Wu, Shang Zhang, Shunyao Zhang, Yongan Li, Chaojian Boominathan, Vivek Veeraraghavan, Ashok Li, Ziyun Lin, Yingyan Rice Univ Houston TX 77005 USA Meta Real Labs Redmond WA USA

ISBN: (纸本)9781450386104

Eye tracking has become an essential human-machine interaction modality for providing immersive experience in numerous virtual and augmented reality (VR/AR) applications desiring high throughput (e.g., 240 FPS), small-form, and enhanced visual privacy. However, existing eye tracking systems are still limited by their: (1) large form-factor largely due to the adopted bulky lens-based cameras;(2) high communication cost required between the camera and backend processor;and (3) potentially concerned low visual privacy, thus prohibiting their more extensive applications. To this end, we propose, develop, and validate a lensless FlatCam-based eye tracking algorithm and accelerator co-design framework dubbed EyecoD to enable eye tracking systems with a much reduced form-factor and boosted system efficiency without sacrificing the tracking accuracy, paving the way for next-generation eye tracking solutions. On the system level, we advocate the use of lensless FlatCams instead of lens-based cameras to facilitate the small form-factor need in mobile eye tracking systems, which also leaves rooms for a dedicated sensing-processor co-design to reduce the required camera-processor communication latency. On the algorithm level, EyecoD integrates a predict-then-focus pipeline that first predicts the region-of-interest (ROI) via segmentation and then only focuses on the ROI parts to estimate gaze directions, greatly reducing redundant computations and data movements. On the hardware level, we further develop a dedicated accelerator that (1) integrates a novel workload orchestration between the aforementioned segmentation and gaze estimation models, (2) leverages intra-channel reuse opportunities for depth-wise layers, (3) utilizes input feature-wise partition to save activation memory size, and (4) develops a sequential-write-parallel-read input buffer to alleviate the bandwidth requirement for the activation global buffer. On-silicon measurement and extensive experiments validate

关键词： Eye Tracking Systems VR/AR algorithm-hardware co-design

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The Mondrian Data Engine 17

The Mondrian Data Engine

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44th Annual International Symposium on computer Architecture (ISCA)

作者： Drumond, Mario Daglis, Alexandros Mirzadeh, Nooshin Ustiugov, Dmitrii Picorel, Javier Falsafi, Babak Grot, Boris Pnevmatikatos, Dionisios Ecole Polytech Fed Lausanne EcoCloud Lausanne Switzerland Univ Edinburgh Edinburgh Midlothian Scotland FORTH ICS & ECE TUC Edinburgh Midlothian Scotland

ISBN: (纸本)9781450348928

The increasing demand for extracting value out of ever-growing data poses an ongoing challenge to system designers, a task only made trickier by the end of Dennard scaling. As the performance density of traditional CPU-centric architectures stagnates, advancing compute capabilities necessitates novel architectural approaches. Near-memory processing (NMP) architectures are reemerging as promising candidates to improve computing efficiency through tight coupling of logic and memory. NMP architectures are especially fitting for data analytics, as they provide immense bandwidth to memory-resident data and dramatically reduce data movement, the main source of energy consumption. Modern data analytics operators are optimized for CPU execution and hence rely on large caches and employ random memory accesses. In the context of NMP, such random accesses result in wasteful DRAM row buffer activations that account for a significant fraction of the total memory access energy. In addition, utilizing NMP's ample bandwidth with fine-grained random accesses requires complex hardware that cannot be accommodated under NMP's tight area and power constraints. Our thesis is that efficient NMP calls for an algorithm-hardware co-design that favors algorithms with sequential accesses to enable simple hardware that accesses memory in streams. We introduce an instance of such a co-designed NMP architecture for data analytics, the Mondrian Data Engine. compared to a CPU-centric and a baseline NMP system, the Mondrian Data Engine improves the performance of basic data analytics operators by up to 49x and 5x, and efficiency by up to 28x and 5x, respectively.

关键词： Near-memory processing sequential memory access algorithm-hardware co-design

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Boosting the Performance of CNN Accelerators with Dynamic Fine-Grained Channel Gating 52

Boosting the Performance of CNN Accelerators with Dynamic Fi...

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52nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： Hua, Weizhe Zhou, Yuan De Sa, Christopher Zhang, Zhiru Suh, G. Edward Cornell Univ Ithaca NY 14850 USA

ISBN: (纸本)9781450369381

This paper proposes a new fine-grained dynamic pruning technique for CNN inference, named channel gating, and presents an accelerator architecture that can effectively exploit the dynamic sparsity. Intuitively, channel gating identifies the regions in the feature map of each CNN layer that contribute less to the classification result and turns off a subset of channels for computing the activations in these less important regions. Unlike static network pruning, which removes redundant weights or neurons prior to inference, channel gating exploits dynamic sparsity specific to each input at run time and in a structured manner. To maximize compute savings while minimizing accuracy loss, channel gating learns the gating thresholds together with weights automatically through training. Experimental results show that the proposed approach can significantly speed up state-of-the-art networks with a marginal accuracy loss, and enable a trade-off between performance and accuracy. This paper also shows that channel gating can be supported with a small set of extensions to a CNN accelerator, and implements a prototype for quantized ResNet-18 models. The accelerator shows an average speedup of 2.3x for ImageNet when the theoretical FLOP reduction is 2.8x, indicating that the hardware can effectively exploit the dynamic sparsity exposed by channel gating.

关键词： neural networks dynamic pruning algorithm-hardware co-design

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