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A METHODOLOGY FOR ALGORITHM REGULARIZATION AND MAPPING INTO TIME-OPTIMAL VLSI ARRAYS

PARALLEL COMPUTING 1993年第1期19卷 33-61页

作者： BARADA, H ELAMAWY, A LOUISIANA STATE UNIV BATON ROUGELA 70803

This paper provides a fairly comprehensive treatment of a broad class of algorithms as it pertains to systolic implementation. We describe some formal algorithmic transformations that can be utilized to map regular and some irregular compute-bound algorithms into the best-fit time-optimal systolic architectures. This methodology uses the concept of dependence vectors to order in time and space the index points representing the algorithm. However, by differentiating between two types of dependence vectors, the ordering procedure is allowed to be flexible and time optimal. Furthermore, the approach reported here deals with variable as well as fixed dependence vectors and does not put constraints on the topology or dimensionality of the target architecture. The ordered index points are represented by nodes in a diagram called Systolic Precedence Diagram (SPD). The SPD is transformed into a directed graph called the Systolic Directed Graph (SDG) which can be projected along defined directions to obtain the target architectures. If more than one valid projection direction exist, different designs are obtained. The resulting architectures are then evaluated to determine if an improvement in the performance can be achieved by increasing PE fan-out. If so, the method provides the corresponding systolic implementation. The methodology has been tried on many signal processing, image processing, and graph theory algorithms and new arrays were designed as a result. In this paper, the methodology is illustrated by mapping three problems, namely, vector-matrix multiplication, matrix-matrix multiplication, and transitive closure problems into many planar and nonplanar time-optimal VLSI arrays.

关键词： SYSTOLIC IMPLEMENTATION GRAPH METHODOLOGY FOR REGULARIZING DATA FLOW algorithmic transformations SYSTOLIC ARCHITECTURE TIME-OPTIMAL VLSI ARRAYS MAPPING

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Scalable parallel processor array for Jacobi-type matrix computations

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INTEGRATION-THE VLSI JOURNAL 1995年第1期20卷 41-61页

作者： vanDijk, HW Hekstra, GJ Deprettere, EF Department of Electrical Engineering Delft University of Technology P.O. Box 5031 2628 CD Delft The Netherlands

This paper addresses the problem of designing a family of potential processor arrays for the execution of the so-called Jacobi algorithms. It extends the more familiar problem of designing a single fixed-size processor array for a particular program and it is parametrised with respect to size in two ways. Firstly, the program is no longer a particular one but is a member from a set of related programs. Secondly, the processor array itself is now also parametrised with respect to its dimension and size. There are thus three parameters involved, one to identify the program, one to select the program's size and one for the possible dimensions/sizes of the array implementation. The approach proposed in this paper is to use the design model and methods which have been used so far for the 'one array for one program' design problem and provide - instead of a processor array - a parameter controlled generic processor and a program to generate the control for the execution of a selected program on a specific array of such processors. This allows a user to compose an array out of a number of these generic processors and generate the necessary control signals actually executing the selected program. The control signals propagate down the array and instruct each processor how to process the incoming data. The control is hierarchical in the sense that a processor decodes and processes the incoming control signals so as to fix internal behaviour. The more processors are used, the less sequential the execution of the program will be. The generic processor uses Cordic arithmetic for its processing part and in addition to this it consists of a communication part and an internal memory bank. Communication between processors is a-synchronous while the internal timing is clocked.

关键词： Jacobi-algorithms algorithmic transformations adaptive algorithms parallel processing algorithm partitioning tesselation

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Efficient FPGA Mapping of Pipeline SDF FFT Cores

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2017年第9期25卷 2486-2497页

作者： Ingemarsson, Carl Kallstrom, Petter Qureshi, Fahad Gustafsson, Oscar Linkoping Univ Dept Elect Engn SE-58183 Linkoping Sweden Tampere Univ Technol Dept Pervas Comp FI-33101 Tampere Finland

In this paper, an efficient mapping of the pipeline single-path delay feedback (SDF) fast Fourier transform (FFT) architecture to field-programmable gate arrays (FPGAs) is proposed. By considering the architectural features of the target FPGA, significantly better implementation results are obtained. This is illustrated by mapping an R22SDF 1024-point FFT core toward both Xilinx Virtex-4 and Virtex-6 devices. The optimized FPGA mapping is explored in detail. algorithmic transformations that allow a better mapping are proposed, resulting in implementation achievements that by far outperforms earlier published work. For Virtex-4, the results show a 350% increase in throughput per slice and 25% reduction in block RAM (BRAM) use, with the same amount of DSP48 resources, compared with the best earlier published result. The resulting Virtex-6 design sees even larger increases in throughput per slice compared with Xilinx FFT IP core, using half as many DSP48E1 blocks and less BRAM resources. The results clearly show that the FPGA mapping is crucial, not only the architecture and algorithm choices.

关键词： algorithmic transformations fast Fourier transform (FFT) field-programmable gate arrays (FPGAs) hardware mapping single-path delay feedback (SDF)

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algorithmic transformation techniques for efficient exploration of alternative application instances

Algorithmic transformation techniques for efficient explorat...

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10th International Symposium on Hardware/Software Codesign (CODES 2002)

作者： Stefanov, T Kienhuis, B Deprettere, E Leiden Univ Leiden Inst Adv Comp Sci Leiden Netherlands

ISBN: (纸本)1581135424

Following the Y-chart paradigm for designing a system, an application and an architecture are modeled separately and mapped onto each other in an explicit design step. Next, a performance analysis for alternative application instances, architecture instances and mappings has to be done, thereby exploring the design space of the target system. Deriving alternative application instances is not trivially done. Nevertheless, many instances of a single application exist that are worth to be derived for exploration. In this paper, we present algorithmic transformation techniques for systematic and fast generation of alternative application instances that express task-level concurrency hidden in an application in some degree of explicitness. These techniques help a system designer to speedup significantly the design space exploration process.

关键词： system-level design design space exploration application instances algorithmic transformations

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algorithmic transformation techniques for efficient exploration of alternative application instances 02

Algorithmic transformation techniques for efficient explorat...

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Proceedings of the tenth international symposium on Hardware/software codesign

作者： Todor Stefanov Bart Kienhuis Ed Deprettere Leiden University The Netherlands

ISBN: (纸本)9781581135428

关键词： design space exploration algorithmic transformations system-level design application instances

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