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An embedded multi-core biometric identification system

MICROPROCESSORS AND MICROSYSTEMS 2011年第5期35卷 510-521页

作者： Danese, G. Giachero, M. Leporati, F. Nazzicari, N. Univ Pavia Dip Informat & Sistemist I-27100 Pavia Italy Univ Pavia Microcomp Lab I-27100 Pavia Italy

Biometric identification systems exploit automated methods of recognition based on physiological or behavioural characteristics. Among these, fingerprints are very reliable as biometric identifiers. In order to build embedded systems performing real-time authentication, a fast computational unit for image processing is required. In this paper we propose a parallel architecture that efficiently implements the high computationally demanding core of a matching algorithm based on Band-Limited Phase Only spatial Correlation (BLPOC), performed by two concurrent computational units implemented onto a Stratix II Altera family FPGA. The device here described is competitive with similar hardware solutions described in literature and outperforms the elaboration capabilities of general-purpose processors. (C) 2011 Elsevier B.V. All rights reserved.

关键词： Multiple-processor systems algorithms implemented in hardware Field programmable gate arrays Real-time and embedded systems Biometric authentication

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FPGA-lased Virtual Screening Acceleration of Rigid-Molecule locking

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COMPUTING IN SCIENCE & ENGINEERING 2013年第6期15卷 64-72页

作者： Navarro, Denis Lucia, Oscar Gil-Narvion, Jose M. Jimenez, Oscar Univ Zaragoza Dept Elect Engn & Commun E-50009 Zaragoza Spain Univ Zaragoza Inst Biocomputat & Phys Complex Syst E-50009 Zaragoza Spain

Virtual screening is a key process used to identify the most suitable molecule combinations when developing a new drug. Molecule docking is a commonly used method to analyze molecule structures and requires computing large databases to identify possible affinities between molecules. The special-purpose, field-programmable gate array (FPGA)-based Janus supercomputer accelerates the virtual screening process.

关键词： Field Programmable Gate Arrays Acceleration Computer Architecture Signal Processing algorithms Databases Virtual Environments Three Dimensional Displays Special Purpose hardware Field Programmable Gate Arrays Acceleration Computer Architecture Signal Processing algorithms Databases Virtual Environments Three Dimensional Displays Scientific Computing hardware Description Languages algorithms implemented in hardware

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Majority-Logic, its applications, and atomic-scale embodiments

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COMPUTERS & ELECTRICAL ENGINEERING 2020年 83卷 106562-106562页

作者： Parhami, Behrooz Abedi, Dariush Jaberipur, Ghassem Univ Calif Santa Barbara Dept Elect & Comp Engn Santa Barbara CA 93106 USA Shahid Beheshti Univ Dept Comp Sceince & Engn Tehran *** Iran Inst Res Fundamental Sci IPM Sch Comp Sci Tehran Iran

Today's computing is increasingly data-intensive, heralding the age of big data. With greater data volumes, come the needs for faster processing, greater storage capacity, and expanded communication bandwidth, all of which imply the expenditure of more energy. Thus, energy efficiency, already a major design consideration, will assume broader significance in the coming years. As important as storage and communications are, our focus in this paper is on better technology to reduce the computation (logic manipulation) power. We review majority logic, a special case of threshold logic, show how a number of common arithmetic/logic operations can be performed using the majority-gate primitive, and review an impressive array of atomic-scale logic technologies that are particularly efficient in realizing the majority or minority function. We conclude that a combination of orders of magnitude energy reduction by virtue of the technology used and implementation strategies that lead to comparable complexity in terms of majority gates when contrasted with currently used circuit primitives (AND, OR, XOR, NOT, mux) leads to energy-efficient realization of arithmetic/logic functions suitable for use in the age of big data. (C) 2020 Published by Elsevier Ltd.

关键词： algorithms implemented in hardware Cellular arrays and automata High-speed arithmetic Logic design styles Low-power design Performance analysis and design aids

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Adapting Computer Arithmetic Structures to Sustainable Supercomputing in Low-Power, Majority-Logic Nanotechnologies

IEEE TRANSACTIONS ON SUSTAINABLE COMPUTING

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IEEE TRANSACTIONS ON SUSTAINABLE COMPUTING 2018年第4期3卷 262-273页

作者： Jaberipur, Ghassem Parhami, Behrooz Abedi, Dariush Shahid Beheshti Univ Dept Comp Sci & Engn Tehran *** Iran Inst Res Fundamental Sci IPM Sch Comp Sci Tehran Iran Univ Calif Santa Barbara Dept Elect & Comp Engn Santa Barbara CA 93106 USA

Petascale supercomputers are already pushing power boundaries that can be supplied or dissipated cost-effectively;greater challenges await us in the era of exascale machines. We are thus motivated to study methods of reducing the energy cost of arithmetic operations, which can be substantial in numerically intensive applications. Additionally, being both a widely-used operation in itself and an important building block for synthesizing other arithmetic operations, has received much attention in this regard. Circuit and energy costs of fast adders are dominated by their fast carry networks. The availability of simple and energy-efficient majority function in certain emerging nanotechnologies (such as quantum-dot cellular automata, single-electron tunneling, tunneling phase logic, magnetic tunnel junction, nanoscale bar magnets, and memristors) has motivated our work to reformulate the carry recurrence in terms of fully-utilized majority elements, with all three inputs usefully employed. We compare our novel designs and resulting circuits to prior proposals based on 3-input majority elements in quantum-dot cellular automata, demonstrating advantages in both speed and circuit complexity. We also show that the performance and cost advantages carry over to at least one other emerging, energy-efficient technology, single-electron tunneling, raising hopes for achieving similar benefits with other technologies, which we review very briefly.

关键词： High-speed arithmetic performance analysis and design aids cellular arrays and automata algorithms implemented in hardware logic design styles low-power design

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Dynamic Sparse Attention for Scalable Transformer Acceleration

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IEEE TRANSACTIONS ON COMPUTERS 2022年第12期71卷 3165-3178页

作者： Liu, Liu Qu, Zheng Chen, Zhaodong Tu, Fengbin Ding, Yufei Xie, Yuan Univ Calif Santa Barbara Santa Barbara CA 93106 USA

Transformers are the mainstream of NLP applications and are becoming increasingly popular in other domains such as Computer Vision. Despite the improvements in model quality, the enormous computation costs make Transformers difficult at deployment, especially when the sequence length is large in emerging applications. Processing attention mechanism as the essential component of Transformer is the bottleneck of execution due to the quadratic complexity. Prior art explores sparse patterns in attention to support long sequence modeling, but those pieces of work are on static or fixed patterns. We demonstrate that the sparse patterns are dynamic, depending on input sequences. Thus, we propose the Dynamic Sparse Attention (DSA) that can efficiently exploit dynamic sparse patterns in attention. Compared with other methods, our approach can achieve better trade-offs between accuracy and model complexity. Moving forward, we identify challenges and provide solutions to implement DSA on existing hardware (GPUs) and specialized hardware in order to achieve practical speedup and efficiency improvements for Transformer execution.

关键词： algorithms implemented in hardware types and design styles integrated circuits < B hardware special-purpose and application-based systems computer systems organization

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A Fully-Pipelined hardware Design for Gaussian Mixture Models

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IEEE TRANSACTIONS ON COMPUTERS 2017年第11期66卷 1837-1850页

作者： He, Conghui Fu, Haohuan Guo, Ce Luk, Wayne Yang, Guangwen Tsinghua Univ Dept Comp Sci & Technol Beijing 100044 Shi Peoples R China Tsinghua Univ Minist Educ Key Lab Earth Syst Modeling Beijing 100044 Shi Peoples R China Tsinghua Univ Dept Earth Syst Sci Beijing 100044 Shi Peoples R China Tsinghua Univ Inst High Performance Comp Beijing 100044 Shi Peoples R China Imperial Coll London SW7 2AZ England

Gaussian Mixture Models (GMMs) are widely used in many applications such as data mining, signal processing and computer vision, for probability density modeling and soft clustering. However, the parameters of a GMM need to be estimated from data by, for example, the Expectation-Maximization algorithm for Gaussian Mixture Models (EM-GMM), which is computationally demanding. This paper presents a novel design for the EM-GMM algorithm targeting reconfigurable platforms, with five main contributions. First, a pipeline-friendly EM-GMM with diagonal covariance matrices that can easily be mapped to hardware architectures. Second, a function evaluation unit for Gaussian probability density based on fixed-point arithmetic. Third, our approach is extended to support a wide range of dimensions or/and components by fitting multiple pieces of smaller dimensions onto an FPGA chip. Fourth, we derive a cost and performance model that estimates logic resources. Fifth, our dataflow design targeting the Maxeler MPC-X2000 with a Stratix-5SGSD8 FPGA can run over 200 times faster than a 6-core Xeon E5645 processor, and over 39 times faster than a Pascal TITAN-X GPU. Our design provides a practical solution to applications for training and explores better parameters for GMMs with hundreds of millions of high dimensional input instances, for low-latency and high-performance applications.

关键词： Gaussian mixture model expectation maximization high performance computing data flow engine reconfigurable hardware algorithms implemented in hardware

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Tree parity machine rekeying architectures

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IEEE TRANSACTIONS ON COMPUTERS 2005年第4期54卷 421-427页

作者： Volkmer, M Wallner, S Hamburg Univ Technol Dept Comp Engn 6 D-21073 Hamburg Germany

The necessity of securing the communication between hardware components in embedded systems becomes increasingly important with regard to the secrecy of data and particularly its commercial use. We suggest a low-cost (i.e., small logic-area) solution for flexible security levels and short key lifetimes. The basis is an approach for symmetric key exchange using the synchronization of Tree Parity Machines. Fast successive key generation enables a key exchange within a few milliseconds, given realistic communication channels with a limited bandwidth. For demonstration, we evaluate characteristics of a standard-cell ASIC design realization as IP-core in 0.18mu-technology.

关键词： security authentication algorithms implemented in hardware ubiquitous computing pervasive computing

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An Automated Framework for Accelerating Numerical algorithms on Reconfigurable Platforms Using Algorithmic/Architectural Optimization

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IEEE TRANSACTIONS ON COMPUTERS 2009年第12期58卷 1654-1667页

作者： Kim, Jung Sub Deng, Lanping Mangalagiri, Prasanth Irick, Kevin Sobti, Kanwaldeep Kandemir, Mahmut Narayanan, Vijaykrishnan Chakrabarti, Chaitali Pitsianis, Nikos Sun, Xiaobai Penn State Univ Dept Comp Sci & Engn University Pk PA 16802 USA Arizona State Univ Dept Elect Engn Tempe AZ 85287 USA Duke Univ Dept Comp Sci Durham NC 27708 USA

This paper describes TANOR, an automated framework for designing hardware accelerators for numerical computation on reconfigurable platforms. Applications utilizing numerical algorithms on large-size data sets require high-throughput computation platforms. The focus is on N-body interaction problems which have a wide range of applications spanning from astrophysics to molecular dynamics. The TANOR design flow starts with a MATLAB description of a particular interaction function, its parameters, and certain architectural constraints specified through a graphical user interface. Subsequently, TANOR automatically generates a configuration bitstream for a target FPGA along with associated drivers and control software necessary to direct the application from a host PC. Architectural exploration is facilitated through support for fully custom fixed-point and floating-point representations in addition to standard number representations such as single-precision floating point. Moreover, TANOR enables joint exploration of algorithmic and architectural variations in realizing efficient hardware accelerators. TANOR's capabilities have been demonstrated for three different N-body interaction applications: the calculation of gravitational potential in astrophysics, the diffusion or convolution with Gaussian kernel common in image processing applications, and the force calculation with vector-valued kernel function in molecular dynamics simulation. Experimental results show that TANOR-generated hardware accelerators achieve lower resource utilization without compromising numerical accuracy, in comparison to other existing custom accelerators.

关键词： algorithms implemented in hardware reconfigurable hardware signal processing systems numerical algorithms

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A Gaussian noise generator for hardware-based simulations

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IEEE TRANSACTIONS ON COMPUTERS 2004年第12期53卷 1523-1534页

作者： Lee, DU Luk, W Villasenor, JD Cheung, PYK Univ London Imperial Coll Sci Technol & Med Dept Comp London England Univ Calif Los Angeles Dept Elect Engn Los Angeles CA 90095 USA Univ London Imperial Coll Sci Technol & Med Dept Elect & Elect Engn London England

hardware simulation offers the potential of improving code evaluation speed by orders of magnitude over workstation or PC-based simulation. We describe a hardware-based Gaussian noise generator used as a key component in a hardware simulation system, for exploring channel code behavior at very low bit error rates (BERs) in the range of 10(-9) to 10(-10). The main novelty is the design and use of nonuniform piecewise linear approximations in computing trigonometric and logarithmic functions. The parameters of the approximation are chosen carefully to enable rapid computation of coefficients from the inputs while still retaining high fidelity to the modeled functions. The output of the noise generator accurately models a true Gaussian Probability Density Function (PDF) even at very high sigma values. Its properties are explored using: 1) several different statistical tests, including the chi-square test and the Anderson-Darling test, and 2) an application for decoding of Low-Density Parity-Check (LDPC) codes. An implementation at 133MHz on a Xilinx Virtex-II XC2V4000-6 FPGA produces 133 million samples per second, which is seven times faster than a 2.6GHz Pentium-IV PC;another implementation on a Xilinx Spartan-IIE XC2S300E-7 FPGA at 62MHz is capable of a three times speedup. The performance can be improved by exploiting parallelism: An XC2V4000-6 FPGA with nine parallel instances of the noise generator at 105MHz can run 50 times faster than a 2.6GHz Pentium-IV PC. We illustrate the deterioration of clock speed with the increase in the number of instances.

关键词： algorithms implemented in hardware error-checking gate arrays simulation

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Bounding Variable Values and Round-Off Effects Using Handelman Representations

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2011年第11期30卷 1691-1704页

作者： Boland, David Constantinides, George A. Univ London Imperial Coll Sci Technol & Med Dept Elect & Elect Engn Circuits & Syst Res Grp London SW7 2BT England

The precision used in an algorithm affects the error and performance of individual computations, the memory usage, and the potential parallelism for a fixed hardware budget. This paper describes a new method to determine the minimum precision required to meet a given error specification for an algorithm consisting of the basic algebraic operations. Using this approach, it is possible to significantly reduce the computational word-length in comparison to existing methods, and this can lead to superior hardware designs. We demonstrate the proposed procedure on an iteration of the conjugate gradient algorithm, achieving proofs of bounds that can translate to global word-length savings ranging from a few bits to proving the existence of ranges that must otherwise be assumed to be unbounded when using competing approaches. We also achieve comparable bounds to recent literature in a small fraction of the execution time, with greater scalability.

关键词： algorithms implemented in hardware numerical analysis optimization performance analysis and design aids

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