检索结果-内蒙古大学图书馆

Kerneltron: Support vector "machine" in silicon

IEEE TRANSACTIONS ON NEURAL NETWORKS 2003年第5期14卷 1426-1434页

作者： Genov, R Cauwenberghs, G Johns Hopkins Univ Dept Elect & Comp Engn Baltimore MD 21218 USA

Detection of complex objects in streaming video poses two fundamental challenges: training from sparse data with proper generalization across variations in the object class and the environment;and the computational power required of the trained classifier running real-time. The Kerneltron supports the generalization performance of a support vector machine (SVM) and offers the bandwidth and efficiency of a massively parallel architecture. The mixed-signal very large-scale integration (VLSI) processor is dedicated to the most intensive of SVM operations: evaluating a kernel over large numbers of vectors in high dimensions. At the core of the Kerneltron is an internally analog, fine-grain computational array. performing externally digital inner-products between an incoming vector and each of the stored support vectors. The three-transistor unit cell in the array combines single-bit dynamic storage, binary multiplication, and zero-latency analog accumulation. Precise digital outputs are obtained through oversampled quantization of the analog array outputs combined with bit-serial unary encoding of the digital inputs. The 256 input, 128 vector Kerneltron measures 3 min x 3 mm in 0.5 mum CMOS, delivers 6.5 GMACS throughput at 5.9 mW power, and attains 8-bit output resolution.

关键词： analog array processors analog-to-digital conversion (ADC) charge-injection device (CID) dynamic random-access memory (DRAM) matrix-vector multiplication (MVM) oversampling quantization pattern recognition support vector machines (SVMs) vector quantization (VQ)

来源：评论

学校读者我要写书评

暂无评论

Silicon support vector machine with on-line learning

引用

INTERNATIONAL JOURNAL OF PATTERN RECOGNITION AND ARTIFICIAL INTELLIGENCE 2003年第3期17卷 385-404页

作者： Genov, R Chakrabartty, S Cauwenberghs, G Univ Toronto Dept Elect & Comp Engn Toronto ON M5S 3G4 Canada Johns Hopkins Univ Dept Elect & Comp Engn Baltimore MD 21218 USA

Training of support vector machines (SVMs) amounts to solving a quadratic programming problem over the training data. We present a simple on-line SVM training algorithm of complexity approximately linear in the number of training vectors, and linear in the number of support vectors. The algorithm implements an on-line variant of sequential minimum optimization (SMO) that avoids the need for adjusting select pairs of training coefficients by adjusting the bias term along with the coefficient of the currently presented training vector. The coefficient assignment is a function of the margin returned by the SVM classifier prior to assignment, subject to inequality constraints. The training scheme lends efficiently to dedicated SVM hardware for real-time pattern recognition, implemented using resources already provided for run-time operation. Performance gains are illustrated using the Kerneltron, a massively parallel mixed-signal VLSI processor for kernel-based real-time video recognition.

关键词： support vector machine (SVM) large margin classifiers quadratic programming (QP) sequential minimum optimization (SMO) matrix-vector multiplication (MVM) pattern recognition kernel machines analog array processors

来源：评论

学校读者我要写书评

暂无评论

Silicon support vector machine with on-line learning

Silicon support vector machine with on-line learning

引用

1st International Workshop on Pattern Recognition with Support Vector Machines

作者： Genov, R Chakrabartty, S Cauwenberghs, G Univ Toronto Dept Elect & Comp Engn Toronto ON M5S 3G4 Canada Johns Hopkins Univ Dept Elect & Comp Engn Baltimore MD 21218 USA

来源：评论

学校读者我要写书评

暂无评论

Charge-mode parallel architecture for vector-matrix multiplication

引用

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-analog AND DIGITAL SIGNAL PROCESSING 2001年第10期48卷 930-936页

作者： Genov, R Cauwenberghs, G Johns Hopkins Univ Dept Elect & Comp Engn Baltimore MD 21218 USA

An internally analog, externally digital architecture for parallel vector-matrix multiplication is presented. A three-transistor unit cell combines a single-bit dynamic random-access memory and a charge injection device binary multiplier and analog accumulator. Digital multiplication of variable resolution is obtained with bit-serial inputs and bit-parallel storage of matrix elements, by combining quantized outputs from multiple rows of cells over time. A prototype 512 x 128 vector-matrix multiplier on a single 3 mm x 3 mm chip fabricated in standard 0.5-mum CMOS technology achieves 8-bit effective resolution and dissipates 0.5 pJ per multiply-accumulate.

关键词： analog array processors analog-to-digital conversion (ADC) charge-injection device (CID) dynamic random-access memory (DRAM) support vector machines (SVM) vector-matrix multiplication (VMM) vector quantization (VQ)

来源：评论

学校读者我要写书评

暂无评论

A new cell output nonlinearity for dense cellular nonlinear network integration

引用

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS 2001年第3期48卷 272-280页

作者： Paasio, A Halonen, K Helsinki Univ Technol Elect Circuit Design Lab Helsinki Finland

A new approach for designing a cellular nonlinear network (CNN) cell is introduced. The method can be used when the processed images are bipolar, i,e., black and white. A simple circuit realization is introduced that can be applied when building up the analog part of the cell. The cell output nonlinearity is an easily realizable positive range high gain sigmoid, Moreover, a state limited model is adopted to decrease the complexity of the design. The coefficient budding blocks are simple, and also because these blocks introduce an almost error free multiplication by zero, the corresponding devices can be made relatively small due to relaxed coefficient accuracy requirements. This approach yields a very small cell area on silicon and can be used,vith inexpensive digital CMOS processes. Simulation results are given for both static and dynamic behavior of the proposed structure. The dynamic simulation shows very fast convergence time compared to other reported approaches for CNN very large scale integration implementation.

关键词： analog array processors cellular nonlinear networks positive range high gain

来源：评论

学校读者我要写书评

暂无评论

A 0.8-mu m CMOS two-dimensional programmable mixed-signal focal-plane array processor with on-chip binary imaging and instructions storage

引用

IEEE JOURNAL OF SOLID-STATE CIRCUITS 1997年第7期32卷 1013-1026页

作者： DominguezCastro, R Espejo, S RodriguezVazquez, A Carmona, RA Foldesy, P Zarandy, A Szolgay, P Sziranyi, T Roska, T HUNGARIAN ACAD SCI INST COMP & AUTOMATANALOG & NEURAL COMP LABH-1111 BUDAPESTHUNGARY

This paper presents a CMOS chip for the parallel acquisition and concurrent analog processing of two-dimensional (2-D) binary images. Its processing function is determined by a reduced set of 19 analog coefficients whose values are programmable with 7-b accuracy. The internal programming signals are analog, but the external control interface is fully digital. On-chip nonlinear digital-to-analog converters (DAC's) map digitally coded weight values into analog control signals, using feedback to predistort their transfer characteristics in accordance to the response of the analog programming circuitry. This strategy cancels out the nonlinear dependence of the analog circuitry with the programming signal and reduces the influence of interchip technological parameters random fluctuations. The chip includes a small digital RAM memory to store eight sets of processing parameters in the periphery of the cell array and four 2-D binary images spatially distributed over the processing array. It also includes the necessary control circuitry to realize the stored instructions in any order and also to realize programmable logic operations among images. The chip architecture is based on the cellular neural/nonlinear network universal machine (CNN-UM). It has been fabricated in a 0.8-mu m single-poly double-metal technology and features 2-mu s operation speed (time required to process an image) and around 7-b accuracy in the analog processing operations.

关键词： analog array processors cellular neural networks focal plane processors vision chips

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：