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analog decoding using a gradient-type neural network

IEEE TRANSACTIONS ON NEURAL NETWORKS 1996年第4期7卷 1034-1038页

作者： Ciocoiu, IB Faculty of Electronics and Telecommunications Gheorghe Asachi Technical University of Iasi Iasi Romania

The problem of analog (soft) decision decoding of block codes by means of neural networks is addressed. The proposed solution is based on a recurrent high-order network implementing a special gradient-type system, Simulation results for two different capes are reported, showing improved performances over the classical hard decision decoder.

关键词： hard-decision decoding Block codes Neural network systems simulation analog decoding soft-decision decoding

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Probability stopping criterion for analog decoding of LDPC codes

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The Journal of China Universities of Posts and Telecommunications 2017年第1期24卷 35-39页

作者： Zheng Hao Zhang Shuyi Li Lintao Gao Yuan Shao Liwei School of Information and Electronics Beijing Institute of TechnologyBeijing 100081China School of Telecommunication Engineering Beijing University of Posts and TelecommunicationsBeijing 100876China Research Institute of Beijing Institute of Technology in Zhongshan Zhongshan 528400China

To detect uncorrectable frames and terminate the decoding procedure early, a probability stopping criterion for iterative analog decoding of low density parity check （LDPC） codes is proposed in this paper. By using probabilities of satisfied checks to detect uncorrectable frames and terminate decoding, the proposed criterion could be applied to analog decoders without much structure modifications. Simulation results show that the proposed criterion can reduce the average number of iterations and achieve a better balance in bit error ratio （BER） performance and decoding complexity than other stopping criteria using extrinsic information.

关键词： LDPC codes analog decoding early stopping probability stopping criterion

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Semi-iterative analog turbo decoding

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2007年第6期54卷 1305-1316页

作者： Arzel, Matthieu Lahuec, Cyril Seguin, Fabrice Gnaedig, David Jezequel, Michel ENST F-29238 Brest France TurboConcept F-29280 Plouzane France

Based on multiple-slice turbo codes, a novel semi-iterative analog turbo decoding algorithm and its corresponding decoder architecture are presented. This work paves the way for integrating flexible analog decoders dealing with frame lengths over thousands of bits. The algorithm benefits from a partially continuous exchange of extrinsic information to improve decoding speed and correction performance. The proposed algorithm and architecture are applied to design an analog decoder for double-binary codes. Taking full advantage of multiple slice codes, the on-chip area is shown to be reduced by ten when compared to a conventional fully parallelized analog slice turbo decoder. The reconfigurable analog core area for frames of 40 bits up to 2432 bits is 37 mm(2) in a 0.25-mu m BiCMOS process.

关键词： analog decoding multiple-slice turbo codes turbo codes

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Dynamics and performance analysis of analog iterative decoding for low-density parity-check (LDPC) codes

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IEEE TRANSACTIONS ON COMMUNICATIONS 2006年第1期54卷 61-70页

作者： Hemati, S Banihashemi, AH Carleton Univ BCWS Dept Syst & Comp Engn Ottawa ON K1S 5B6 Canada

Conventional iterative decoding with flooding or parallel schedule can be formulated as a fixed-point problem solved iteratively by a successive substitution (SS) method. In this paper, we investigate the dynamics of a continuous-time (asynchronous) analog implementation of iterative decoding, and show that it can be approximated as the application of the well-known successive relaxation (SR) method for solving the fixed-point problem. We observe that SR with the optimal relaxation factor can considerably improve the error-rate performance of iterative decoding for short low-density parity-check (LDPC) codes, compared with SS. Our simulation results for the application of SR to belief propagation (sum-product) and min-sum algorithms demonstrate improvements of up to about 0.7 dB over the standard SS for randomly constructed LDPC codes. The improvement in performance increases with the maximum number of iterations, and by accordingly reducing the relaxation factor. The asymptotic result, corresponding to an infinite maximum number of iterations and infinitesimal relaxation factor, represents the steady-state performance of analog iterative decoding. This means that under ideal circumstances, continuous-time (asynchronous) analog decoders can outperform their discrete-time (synchronous) digital counterparts by a large margin. Our results also indicate that with the assumption of a truncated Gaussian distribution for the random delays among computational modules, the error-rate performance of the analog decoder, particularly in steady state, is rather independent of the variance of the distribution. The proposed simple model for analog decoding, and the associated performance curves, can be used as an "ideal analog decoder" benchmark for performance evaluation of analog decoding circuits.

关键词： analog decoding asynchronous iterative methods belief propagation (BP) dynamics of iterative decoding iterative decoding low-density parity-check (LDPC) codes min-sum (MS) successive relaxation (SR) successive substitution (SS) sum-product

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Area-efficient analog decoder design for low density parity check codes in deep-space applications

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The Journal of China Universities of Posts and Telecommunications 2017年第4期24卷 69-75页

作者： Zhao Zhe Gao Fei Zheng Hao Yin Xue School of Information and Electronics Beijing Institute of Technology Beijing 100081 China

Area-efficient design methodology is proposed for the analog decoding implementations of the rate-l/2 accumulate repeat-4 jagged-accumulate （AR4JA） low density parity check （LDPC） code. The proposed approach is designed using optimized decoding architecture and regularized routing network, in such a way that the overall wiring overhead is minimized and the silicon area utilization is significantly improved. The prototyping chip used to verily the approach is tully integrated in a four-metal double-poly 0.35 lam complementary metal oxide semiconductor （CMOS） technology, and includes an input-output interface that maximizes the decoder throughput. The decoding core area is 2.02 mm2 with a post-layout area utilization of 80%. The decoder was successfully tested at the maximum data rate of 10 Mbit/s, with a core power consumption of 6.78 mW at 3.3 V, which corresponds to an energy per decoded bit of 0.677 nJ. The proposed analog LDPC decoder with low processing power and high-reliability is suitable lbr space- and power-constrained spacecraft system.

关键词： low density parity check (LDPC) code analog decoding iterative message-passing algorithms hardware efficient area utilization

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Parity-Check Coding Based on Genetic Circuits for Engineered Molecular Communication Between Biological Cells

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IEEE TRANSACTIONS ON COMMUNICATIONS 2018年第12期66卷 6221-6236页

作者： Marcone, Alessio Pierobon, Massimiliano Magarini, Maurizio Politecn Milan Dipartimento Elettron Informaz & Bioingn I-20133 Milan Italy Qualcomm Inc Standardizat Dept D-90411 Nurnberg Germany Univ Nebraska Lincoln Dept Comp Sci & Engn Lincoln NE 68588 USA Consorzio Nazl Interuniv Telecomunicaz I-20133 Milan Italy

Synthetic biology, through genetic circuit engineering in biological cells, is paving the way toward the realization of programmable man-made living devices, able to naturally operate within normally less accessible domains, i.e., the biological and the nanoscale. The control of the information processing and exchange between these engineered-cell devices, based on molecules and biochemical reactions, i.e., molecular communication (MC), will be enabling technologies for the emerging paradigm of the Internet of Bio-Nano Things, with applications ranging from tissue engineering to bioremediation. In this paper, the design of genetic circuits to enable MC links between engineered cells is proposed by stemming from techniques for information coding and inspired by recent studies favoring the efficiency of analog computation over digital in biological cells. In particular, the design of a joint encoder-modulator for the transmission of binary-modulated molecule concentration is coupled with a decoder that computes the a-posteriori log-likelihood ratio of the information bits from the propagated concentration. These functionalities are implemented entirely in the biochemical domain through activation and repression of genes, and biochemical reactions, rather than classical electrical circuits. Biochemical simulations are used to evaluate the proposed design against a theoretical encoder/decoder implementation taking into account impairments introduced by diffusion noise.

关键词： Molecular communication synthetic biology genetic circuit parity-check encoding analog decoding Internet of Bio-Nano Things Hill's function mass action kinetics soft bit biochemical simulation

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Design, simulation, and testing of a CMOS analog decoder for the block length-40 UMTS turbo code

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IEEE TRANSACTIONS ON COMMUNICATIONS 2006年第11期54卷 1973-1982页

作者： Graell i Amat, Alexandre Benedetto, Sergio Montorsi, Guido Vogrig, Daniele Neviani, Andrea Gerosa, Andrea Politecn Torino Dept Elect I-10129 Turin Italy Univ Pompeu Fabra Dept Technol Barcelona 30100 Spain Univ Padua Dept Informat Engn I-35131 Padua Italy

In this paper, we present an all-analog implementation of the rate-1/3, block length 40, universal mobile telecommunications system (UNITS) turbo decoder. The prototype was designed and fabricated in 0.35 mu m complementary metal-oxide-semiconductor technology and operates at 3.3 V. We also introduce a discrete-time first-order model for analog decoders which allows fast bit-error rate simulations, while taking into account circuit transient behavior and component mismatch. The model is applied to the rate-1/3 analog turbo decoder for UNITS defined in the Third Generation Partnership Project standard, and the discrete-time model predictions are compared with the decoder experimental performance and the transistor-level simulations. These results demonstrated that this model can be successfully used as a tool to both predict analog decoder performance and give design guidelines for complex decoders, for which circuit-level simulations are impractical.

关键词： analog decoding device mismatch discrete-time model iterative decoding turbo codes

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CMOS analog MAP decoder for (8,4) Hamming code

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 2004年第1期39卷 122-131页

作者： Winstead, C Dai, J Yu, SH Myers, C Harrison, RR Schlegel, C Univ Alberta Dept Elect & Comp Engn Edmonton AB T6G 2V4 Canada Univ Utah Dept Elect & Comp Engn Salt Lake City UT 84112 USA

Design and, test results for a fully integrated translinear tail-biting MAP error-control decoder are presented. Decoder designs have. been reported for various applications. which make use of analog computation, mostly for Viterbi-style decoders. MAP decoders are more complex, and are necessary components of powerful iterative decoding system such as Turbo codes. analog circuits may require less area and power than digital implementations in, high-speed iterative applications. Our (8,4) Hamming decoder, implemented in an AMI 0.5-mum process. While is the first functioning CMOS analog MAP decoder. designed to operate in subthreshold, the decoder also functions above threshold with a small performance penalty. The chip has been tested at bit rates up to 2 Mb/s, and simulations indicate a top speed of about 10 Mb/s in strong inversion. The decoder circuit size is 0.82. mm(2), and typical power, consumption is 1 mW at 1 Mb/s.

关键词： analog decoding error-control codes iterative decoders maximum a posteriori (MAP) decoding translinear circuits

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A 13.3-Mb/s 0.35-μm CMOS analog turbo decoder IC with a configurable interleaver

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IEEE JOURNAL OF SOLID-STATE CIRCUITS 2003年第11期38卷 2010-2015页

作者： Gaudet, VC Gulak, PG Univ Alberta Dept Elect & Comp Engn Edmonton AB T6G 2V4 Canada Univ Toronto Dept Elect & Comp Engn Toronto ON M5S 3G4 Canada

Circuits and an IC implementation of a four-state, block length 16, three-metal one-poly 0.35mum CMOS analog turbo decoder with a fully programmable interleaver are presented. The IC was tested at 13.3 Mb/s, has a 1.2 mus latency, and consumes 185 mW on a single 3.3-V power supply, resulting in an energy consumption of 13.9 nJ per decoded bit, thus reducing the energy consumption by 70% relative to existing digital turbo decoders. The core area is 1131.2 x 1257.9 mum(2). The addition of swinging buffers could triple the speed and reduce the latency with minimal increase in power consumption by overlapping storage and decoding phases. Mismatch simulations show that the circuits will be viable for decoder lengths up to a few hundred information bits.

关键词： analog decoding iterative decoding turbo codes

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Low-voltage CMOS circuits for analog iterative decoders

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2006年第4期53卷 829-841页

作者： Winstead, C Nguyen, N Gaudet, VC Schlegel, C Utah State Univ Dept Elect & Comp Engn Logan UT 84322 USA Univ Alberta Dept Elect & Comp Engn High Capac Digital Commun Lab HCDC Edmonton AB T6G 2V4 Canada

Iterative decoders, including Turbo decoders, provide near-optimal error protection for various communication channels and storage media. CMOS analog implementations of these decoders offer dramatic savings in complexity and power consumption, compared to digital architectures. Conventional CMOS analog decoders must have supply voltage greater than I V. A new low-voltage architecture is proposed which reduces the required supply voltage by at least 0.4 V. It is shown that the low-voltage architecture can be used to implement the general sum-product algorithm. The low-voltage analog architecture is then useful for implementing Turbo and low-density parity check decoders. The low-voltage architecture introduces new requirements for signal normalization, which are discussed. Measured results for two fabricated low-voltage analog decoders are also presented.

关键词： analog decoding iterative decoding low-density parity check (LDPC) decoder low voltage low power turbo decoder

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