We study analog decoders in an abstract level and show that their dynamic equations can change with message representation domain. This result, which is in contrast with the behavior of conventional discrete-time iter...
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We study analog decoders in an abstract level and show that their dynamic equations can change with message representation domain. This result, which is in contrast with the behavior of conventional discrete-time iterative decoders, is derived based on continuity requirement for messages that are passed between processing nodes in analog decoders. In this letter, this requirement is met by assigning low-pass filters between processing nodes that remain unchanged for different message representation domains.
A built-in self-test (BIST)technique is presented for testing analog iterative decoders. Catastrophic circuit faults are detected by temporarily operating the analog soft gates in a digital mode. Self-testing operatio...
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A built-in self-test (BIST)technique is presented for testing analog iterative decoders. Catastrophic circuit faults are detected by temporarily operating the analog soft gates in a digital mode. Self-testing operations are performed in the digital domain, thereby lowering the cost and complexity compared to alternative mixed-signal BIST approaches. A proof-of-concept CMOS integrated circuit realization of the BIST is also presented. BER measurements show that the added circuits do not interfere with the decoder's performance during normal operation.
A margin propagation (MP) algorithm that can be used for implementing analog decoders for low-density parity check (LDPC) codes is presented. Unlike conventional sum-product analog decoders that rely on translinear op...
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A margin propagation (MP) algorithm that can be used for implementing analog decoders for low-density parity check (LDPC) codes is presented. Unlike conventional sum-product analog decoders that rely on translinear operation of transistors, MP decoders use addition, subtraction and threshold operations, and therefore can be mapped onto different analog circuit topologies (current-mode, charge-mode, or nonelectronic circuits). This brief describes salient properties of the MP decoding algorithm and compares its performance to the sum-product and the min-sum (MS) decoding algorithms. Simulation results demonstrate that MP based LDPC decoders achieve nearly an identical bit error rate performance as their sum-product counterparts and achieve superior performance as compared to the MS decoding algorithm. Results presented in this brief also demonstrate that, when messages in LDPC decoding are corrupted by additive noise, the MP decoding algorithm delivers superior performance compared to its sum-product and MS counterparts.
We present a low power, dual-function encode/decode circuit for a class of reversible low-density parity-check codes. The circuit offers a small silicon footprint, by operating as an analog decoder and reusing resourc...
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We present a low power, dual-function encode/decode circuit for a class of reversible low-density parity-check codes. The circuit offers a small silicon footprint, by operating as an analog decoder and reusing resources to switch into a digital encode mode. In order to achieve this behaviour from a single circuit we have developed mode-switching gates. These logic gates are able to switch between analog (soft) and digital (hard) computation. Only a small overhead in circuit area is required to transform the analog decoder into a full codec. The encode operation can be performed two orders of magnitude faster than the decode operation, making the circuit suitable for full-duplex applications. The low power and small area of the circuit make it an attractive option for battery powered wireless devices. Circuit simulations indicate a decoding latency of 10 mu s with negligible SNR loss with respect to digital sum-product decoders. (C) 2008 Elsevier B.V. All rights reserved.
In this paper, we show an ideal analog min-sum decoder, in the log-likelihood ratio domain, can be considered as a piecewise linear system. Many theoretical aspects of these decoders, thus, can be studied analytically...
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In this paper, we show an ideal analog min-sum decoder, in the log-likelihood ratio domain, can be considered as a piecewise linear system. Many theoretical aspects of these decoders, thus, can be studied analytically. It is also shown that the dynamic equations can become singular for codes with cycles. When it is non-singular, the corresponding dynamic equations can be solved analytically to derive outputs of the decoder. We study the relationship between singularity and error floor and prove that absorption sets with degree two check nodes are singular graphs and under specific conditions the dynamic equations of an analog min-sum decoder can be reduced to that of an absorption set. The proposed approach paves the way for further analytical analysis on the dynamics of analog min-sum decoders and error floor in low-density parity-check codes.
For a special class of convolutional codes, iterative threshold decoding (ITD) has been shown by simulations to achieve the same error rate performance as belief propagation (BP). In order to get a better understandin...
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ISBN:
(纸本)9781479904464
For a special class of convolutional codes, iterative threshold decoding (ITD) has been shown by simulations to achieve the same error rate performance as belief propagation (BP). In order to get a better understanding of these iterative decoding algorithms, we describe ITD and BP as discrete-time dynamical systems. Based on the theory of dynamical systems, we compare the dynamical behavior of ITD and BP. For the special case of a linear dynamical system, the behavior can be completely characterized. In this case we show that the fixed points of both ITD and BP are globally stable but they do not coincide. The analysis is extended to the case of a continuous-time dynamical system, which represents an important step for modeling analog iterative decoders.
This work presents the design and the test results of an analog decoder for the 40-bit block length, rate 1/3, Turbo Code defined in the UMTS standard. The prototype is fully integrated in a three-metal double-poly 0....
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This work presents the design and the test results of an analog decoder for the 40-bit block length, rate 1/3, Turbo Code defined in the UMTS standard. The prototype is fully integrated in a three-metal double-poly 0.35-mu m CMOS technology, and includes an I/O interface that maximizes the decoder throughput. After the successful implementation of proof-of-concept analog iterative decoders by different research groups in both bipolar and CMOS technologies, this is the first reported prototype of an analog decoder for a realistic error-correcting code. The decoder was successfully tested at the maximum data rate defined in the standard (2 Mb/s), with an overall power consumption of 10.3 mW at 3.3 V, going down to 7.6 mW with the decoder core operated at 2 V, and an extremely low energy per decoded bit and trellis state (0.85 nJ for the decoder core alone).
This paper presents a method for decoding high minimal distance (d(min)) short codes, termed Cortex codes. These codes are systematic block codes of rate 1/2 and can have higher d(min) than turbo codes. Despite this c...
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This paper presents a method for decoding high minimal distance (d(min)) short codes, termed Cortex codes. These codes are systematic block codes of rate 1/2 and can have higher d(min) than turbo codes. Despite this characteristic, these codes have been impossible to decode with good performance because, to reach high d(min), several encoding stages are connected through interleavers. This generates a large number of hidden variables and increases the complexity of the scheduling and initialization. However, the structure of the encoder is well suited for analog decoding. A proof-of-concept Cortex decoder for the (8, 4, 4) Hamming code is implemented in subthreshold 0.25-mu m CMOS. It outperforms an equivalent LDPC-like decoder by 1 dB at BER=10(-5) and is 44 percent smaller and consumes 28 percent less energy per decoded bit.
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