Verilog is a Hardware Description Language (HDL) used for VLSI design and modeling. A software-based Verilog simulator running on general purpose computer is the dominant simulation platform. However, the platform is ...
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Verilog is a Hardware Description Language (HDL) used for VLSI design and modeling. A software-based Verilog simulator running on general purpose computer is the dominant simulation platform. However, the platform is throughput limited at simulating next generation designs. Commercial hardware-assisted solutions are proprietary with various limitations. A hardware-assisted platform through the use of an applicationspecific simulation processor is proposed in this paper. Program flow of this processor is driven by HDL simulation semantics. The microprocessor is customized to support Verilog operations with computation using the language's native data types (0, 1, X, Z) from behavioral to gate-level abstraction, including delay and signal strength modeling. Besides, fine-grained parallel event dispatch and hardware-augmented netlist traversing are acceleration features built in the microprocessor. A prototype was built on an FPGA to demonstrate system viability. Benchmarking against a software-based compiled-code simulator had shown up to 9 times simulation time improvement despite having limited basic speed improvement techniques implemented. Capacity scalability can be achieved through parallel processing and memory expansion. The system offers speed improvement over software-based simulator, while retaining the same usability. These leave unbounded room of improvements to meet future simulation needs.
Reconfigurable hardware allows applicationspecific customization of soft microprocessors. Techniques such as removing unused instructions, software emulation of instructions, custom instruction set extensions, and ru...
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ISBN:
(纸本)9781467311854
Reconfigurable hardware allows applicationspecific customization of soft microprocessors. Techniques such as removing unused instructions, software emulation of instructions, custom instruction set extensions, and run-time reconfigurable instructions have been suggested. However, the techniques have largely been studied separately from each other. The contribution of this paper is a classification method enabling integration of these techniques. This allows for generating an application specific microprocessor based system from a given program. The generated microprocessor is optimized with respect to performance per area. The improvement of our methodology is demonstrated for the CoreBench benchmark. The benefit of combining the removal of unused instructions (ISA subsetting) with software emulation of rarely used instructions is shown to increase performance while at the same time reducing resource requirements. Improvement in both area and performance is accomplished thorough simplifying the design allowing an increase in clock frequency for the synthesized soft CPU. Optimizing only by using custom instructions allowed a 12% increase in performance, but also increased resource usage by 6%. Software emulation combined with ISA subsetting allowed area savings of 7%, but only improved performance by 3%. By combining custom instructions, software emulation and ISA subsetting, we achieved an performance improvement of 15% while at the same time reducing resource requirements.
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