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A Faster Algorithm for Enumerating Connected Convex Subgraphs in Acyclic Digraphs

IEEE EMBEDDED SYSTEMS LETTERS 2017年第1期9卷 9-12页

作者： Wang, Shanshan Xiao, Chenglong Liu, Wanjun Liaoning Tech Univ Fuxin 123000 Peoples R China

Subgraph enumeration is one of the most crucial steps involved in the custom instruction identification for application-specific instruction set processors. Generating all connected convex subgraphs from an acyclic digraph is a computationally difficult problem. In this letter, we propose a simple and fast algorithm for enumerating all connected convex subgraphs in acyclic digraphs. Experimental results show that our algorithm outperforms the latest algorithm in the literature. We also present a parallel approach for enumerating all connected convex subgraphs using MapReduce. Results for real world benchmarks covering different application domains reveal that the parallel approach can achieve near linear speedup over the sequential approach.

关键词： application-specific instruction set processors connected convex subgraph custom instructions data flow graph (DFG) MapReduce

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Fast Just-In-Time Translated Simulator for ASIP Design

Fast Just-In-Time Translated Simulator for ASIP Design

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14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)

作者： Prikryl, Zdenek Kroustek, Jakub Hruska, Tomas Kolar, Dusan Brno Univ Technol Fac Informat Technol Brno Czech Republic

ISBN: (纸本)9781424497560

The fast and accurate processor simulator is an essential tool for effective design of modern high-performance application-specific instruction set processors. The nowadays trend of ASIP design is focused on automatic simulator generation based on a processor description in an architecture description language. The simulator is used for testing and validation of designed processor or target application. Furthermore, the simulator can produce the profiling information. This information can aid design space exploration and the processor and target application optimization. In this paper, we present the concept of automatically generated just-in-time translated simulator with the profiling capabilities. This simulator is very fast, and it is generated in a short time. It can be even used for simulation of special applications, such as applications with self-modifying code or applications for systems with external memories. The experimental results can be found at the end of the paper.

关键词： architecture description languages simulation testing application-specific instruction set processors

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Fast Cycle-Accurate Compiled Simulation

Fast Cycle-Accurate Compiled Simulation

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10th IFAC Workshop on Programmable Devices and Embedded Systems (PDeS)

作者： Prikryl, Zdenek Hruska, Tomas Masarik, Karel Husar, Adam Brno Univ Technol Fac Informat Technol CS-61090 Brno Czech Republic

ISBN: (纸本)9783902661951

The embedded systems with application specific instruction set processors, on which specific software runs, has become an inseparable part of our everyday life. Therefore, powerful tools for their development are necessary. Each tool is used in different phases of an embedded system design. One of the key phases is the testing of processor and software functionality. The most used approach in industry is simulation. A simulation can verify that the processor design and software does not contain bugs and that both parts are optimal enough before embedded system realization. The key factor of simulation is its accuracy and speed. In this article a concept of our cycle-accurate compiled simulation is described. The simulator uses such principles which guarantee independence on a host platform, including very good performance and precision. Furthermore, it can simulate a self-modifying code and systems with external memories.

关键词： Hardware/Software co-desing Simulation Embedded systems application-specific instruction set processors

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Fast Cycle-Accurate Compiled Simulation

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IFAC Proceedings Volumes 2010年第24期43卷 76-81页

作者： Zdeněk Přikryl Tomáš Hruška Karel Masařík Adam Husár of Information Technology Brno University of Technology Brno Czech Republic

关键词： Hardware/Software co-desing Simulation Embedded systems application-specific instruction set processors

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Custom-instruction synthesis for ex-tensible-processor platforms

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2004年第2期23卷 216-228页

作者： Sun, F Ravi, S Raghunathan, A Jha, NK Princeton Univ Dept Elect Engn Princeton NJ 08544 USA NEC Labs Amer Princeton NJ 08540 USA

Efficiency and flexibility are critical, but often conflicting, design goals in embedded system design. The recent emergence of extensible processors promises a favorable tradeoff between efficiency and flexibility, while keeping design turnaround times short. Current extensible processor design flows automate several tedious tasks, but typically require designers to manually select the parts of the program that are to be implemented as custom instructions. In this work, we describe an automatic methodology to select custom instructions to augment an extensible processor, in order to maximize its efficiency for a given application program. We demonstrate that the number of custom instruction candidates grows rapidly with program size, leading to a large design space, and that the quality (speedup) of custom instructions varies significantly across this space, motivating the need for the proposed flow. Our methodology features cost functions to guide the custom instruction selection process, as well as static and dynamic pruning techniques to eliminate inferior parts of the design space from consideration. Furthermore, we employ a two-stage process, wherein a limited number of promising instruction candidates are first short-listed using efficient selection criteria, and then evaluated in more detail through cycle-accurate instruction set simulation and synthesis of the corresponding hardware, to identify the custom instruction combinations that result in the highest program speedup or maximize speedup under a given area constraint. We have evaluated the proposed techniques using a state-of-the-art extensible processor platform, in the context of a commercial design flow. Experiments with several benchmark programs indicate that custom processors synthesized using automatic custom instruction selection can result in large improvements in performance (up to 5.4x, an average of 3.4x), energy (up to 4.5x, an average of 3.2x), and energy-delay products (up to 24.2x, an a

关键词： application-specific instruction set processors (ASIP) application-specific programmable processors customization extensible processors instruction selection

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Performance evaluation of network processor architectures:: combining simulation with analytical estimation

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COMPUTER NETWORKS 2003年第5期41卷 641-665页

作者： Chakraborty, S Künzli, S Thiele, L Herkersdorf, A Sagmeister, P Swiss Fed Inst Technol Swiss Fed Inst Technol Comp Engn & Networks Lab CH-8092 Zurich Switzerland IBM Corp Zurich Res Lab CH-8803 Ruschlikon Switzerland

The designs of most systems-on-a-chip (SoC) architectures rely on simulation as a means for performance estimation. Such designs usually start with a parameterizable template architecture, and the design space exploration is restricted to identifying the suitable parameters for all the architectural components. However, in the case of heterogeneous SoC architectures such as network processors the design space exploration also involves a combinatorial aspect-which architectural components are to be chosen, how should they be interconnected, task mapping decisions-thereby increasing the design space. Moreover, in the case of network processor architectures there is also an associated uncertainty in terms of the application scenario and the traffic it will be required to process. As a result, simulation is no longer a feasible option for evaluating such architectures in any automated or semi-automated design space exploration process due to the high simulation times involved. To address this problem, in this paper we hypothesize that the design space exploration for network processors should be separated into multiple stages, each having a different level of abstraction. Further, it would be appropriate to use analytical evaluation frameworks during the initial stages and resort to simulation techniques only when a relatively small set of potential architectures is identified. None of the known performance evaluation methods for network processors have been positioned from this perspective. We show that there are already suitable analytical models for network processor performance evaluation which may be used to support our hypothesis. To this end, we choose a reference system-level model of a network processor architecture and compare its performance evaluation results derived using a known analytical model [Thiele et al., Design space exploration of network processor architectures, in: Proc. 1st Workshop on Network processors, Cambridge, MA, February 2002;Thiele et a

关键词： performance analysis network processors high-performance routers application-specific instruction set processors

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Testování generovaných překladačů jazyka c pro procesory ve vestavěných systémech

Testování generovaných překladačů jazyka c pro proceso...

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作者： Dolíhal, Luděk Brno University of Technology

Vestavěné systémy se staly nepostradatelnými pro náš každodenní život. Jsou to obvykle úzce zaměřená, vysoce optimalizovaná, jednoúčelová zařízení. Já... 详细信息

Vestavěné systémy se staly nepostradatelnými pro náš každodenní život. Jsou to obvykle úzce zaměřená, vysoce optimalizovaná, jednoúčelová zařízení. Jádro vestavěných zařízení obvykle tvoří jeden nebo více aplikačně specifických instrukčních procesorů. Tato disertační práce se zaměřuje na problematiku testování nástrojú pro návrh aplikačně specifických procesorů a následně i samotných aplikačne specifických procesorů. Snahou bylo vytvořit systém, ve kterém bude možné otestovat jednotlivé nástroje, jako například překladač, assembler, disassembler, debugger. Nicméně vyvstává také potřeba provádět složitější testy, například integrační, které zaručí, že mezi jednotlivými nástroji nevzniká nekompatibilita. Autor vytvořil s podporou přůběžně integračního serveru prostředí, které napomáhá odhalování a odstraňování chyb při návrhu aplikačně specifických procesorů a které je navíc do značné míry automatizované.

关键词： Testing compilers continuous integration hardware/software codesign application-specific instruction set processors architecture description languages embedded systems. Testování překladače průběžná integrace hardware/software codesign procesor

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