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IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)

作者： Ngalamou, Lucien Lewis Univ Dept Engn Comp & Math Sci Romeoville IL 60446 USA

ISBN: (纸本)9781665424615

This paper presents an implementation of a singlephase space vector pulse width modulation (SP-SVPWM) IP1 Core suitable for the design of single-phase DC-to-AC converters (inverters). The SP-SVPWM generation uses a RTL2 approach to leverage the real-time implementation of the major concepts behind the IP Core. The design employs RTL-based modern arithmetic algorithms to allow a sinusoidal variation of the switching pulse which controls the power transistors of a single-phase inverter. The value of the switching period depends on the latency of the arithmetic function blocks. Preliminary results of the use of the IP core deployment in an inverter design, resulted in a less than 1% harmonic distortion.

关键词： SP-SVPWM IP Core DC-to-AC Converter arithmetic algorithms Harmonic Distortion

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Efficient realisation of arithmetic algorithms with weighted collection of posibits and negabits

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IET COMPUTERS AND DIGITAL TECHNIQUES 2012年第5期6卷 259-268页

作者： Jaberipur, G. Parhami, B. Shahid Beheshti Univ Dept Elect & Comp Engn Tehran *** Iran Inst Res Fundamental Sci IPM Sch Comp Sci Tehran Iran Univ Calif Santa Barbara Dept Elect & Comp Engn Santa Barbara CA 93106 USA

Most common uses of negatively weighted bits (negabits), normally assuming arithmetic value 21(0) for logical 1(0) state, are as the most significant bit of 2's-complement numbers and negative component in binary signed-digit (BSD) representation. More recently, weighted bit-set (WBS) encoding of generalised digit sets and practice of inverted encoding of negabits (IEN) have allowed for easy handling of any equally weighted mix of negabits and ordinary bits (posibits) via standard arithmetic cells (e.g., half/full adders, compressors, and counters), which are highly optimised for a host of simple and composite figures of merit involving delay, power, and area, and are continually improving due to their wide applicability. In this paper, we aim to promote WBS and IEN as new design concepts for designers of computer arithmetic circuits. We provide a few relevant examples from previously designed logical circuits and redesigns of established circuits such as 2's-complement multipliers and modified booth recoders. Furthermore, we present a modulo-(2(n) + 1) multiplier, where partial products are represented in WBS with IEN. We show that by using standard reduction cells, partial products can be reduced to two. The result is then converted, in constant time, to BSD representation and, via simple addition, to final sum.

关键词： weighted bitset WBS weighted collection logical circuits posibits Logic and switching circuits arithmetic value negatively weighted bits inverted encoding of negabits logic circuits computer arithmetic circuits modulo-(2n+1) multiplier Logic circuits arithmetic algorithms Logic design methods BSD multiplying circuits binary signed digit Digital circuit design, modelling and testing standard reduction cells negabits logic design negative component IEN

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On the Detectability of Hardware Trojans Embedded in Parallel Multipliers 48

On the Detectability of Hardware Trojans Embedded in Paralle...

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48th IEEE International Symposium on Multiple-Valued Logic (ISMVL)

作者： Ito, Akira Ueno, Rei Homma, Naofumi Aoki, Takafumi Tohoku Univ Aoba Ku 2-1-1 Katahira Sendai Miyagi 9808577 Japan

ISBN: (纸本)9781538644645

This paper presents a new method for analyzing the detectability of a hardware Trojan (HT) that has infected parallel multipliers. The proposed method handles the Rare Path Trojan (RPT) that exploits the difficulty in activating a specific path of a parallel multiplier. In this paper we analyze some typical multipliers from the viewpoints of RPT characteristics and insertion/detection possibility. The validity of our criteria is evaluated by multiple regression analysis. Our experimental result indicates that a multiplier based on a redundant binary tree has a larger detectability than other ones.

关键词： hardware trojans arithmetic algorithms multipliers path delay faults

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Parallelism in Computer arithmetic: A Historical Perspective 61

Parallelism in Computer Arithmetic: A Historical Perspective

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61st IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)

作者： Parhami, Behrooz Univ Calif Santa Barbara Dept Elect & Comp Engn Santa Barbara CA 93106 USA

ISBN: (纸本)9781538673928

Many early parallel processing breakthroughs emerged from the quest for faster and higher-throughput arithmetic operations. Additionally, the influence of arithmetic techniques on parallel computer performance can be seen in diverse areas such the bit-serial arithmetic units of early massively parallel SIMD computers, pipelining and pipeline-chaining in vector machines, design of floating-point standards to ensure the accuracy and portability of numerically-intensive programs, and prominence of GPUs in today's top-of-the-line supercomputers. This paper contains a few representative samples of the many interactions and cross-fertilizations between computer-arithmetic and parallel-computation communities by presenting historical perspectives, case studies of state of art and practice, and directions for further collaboration.

关键词： arithmetic algorithms DSP Graphic processors Parallelism Pipelining Recursive circuits Residue arithmetic

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Formal Design of Multiple-Valued arithmetic algorithms over Galois Fields and Its Application to Cryptographic Processor

Formal Design of Multiple-Valued Arithmetic Algorithms over ...

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42nd IEEE International Symposium on Multiple-Valued Logic (ISMVL)

作者： Homma, Naofumi Saito, Kazuya Aoki, Takafumi Tohoku Univ Grad Sch Informat Sci Sendai Miyagi 9808579 Japan

ISBN: (纸本)9780769546735

This paper presents a formal description of multiple-valued arithmetic algorithms over Galois Fields (GFs). Our graph-based method can be applied to any multiple-valued arithmetic circuit over GF(2(m)). The proposed circuit description is formally verified by formula manipulation based on polynomial reduction using Grobner basis. In this paper, we first present the graph representation and its extension. We also present an application of the proposed method to cryptographic processor consisting of GF(2(m)) arithmetic circuits. The target architecture considered here is a round-per-cycle loop architecture commonly used in the design of cryptographic processors. The proposed approach successfully describes the 128-bit datapath and verifies it within 4 minutes.

关键词： arithmetic algorithms formal verification multiple-valued logic computer algebra

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Comparative Analysis of Power Consumption in the Implementation of arithmetic algorithms

Comparative Analysis of Power Consumption in the Implementat...

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Int Joint Conference of 10th IEEE Int Conf on Trust, Security and Privacy in Computing and Communications (TrustCom) / 8th IEEE Int Conf on Embedded Software and Systems (ICESS) / 6th Int Conf on Frontier of Computer Science and Technology (FCST)

作者： Faria, Alexandre Wagner C. de Aguiar, Leandro P. Lara, Daniel D. Loureiro, Antonio A. F. Univ Fed Minas Gerais Dept Comp Sci Belo Horizonte MG Brazil

ISBN: (纸本)9780769546001

Historically, energy management in computer science has been predominantly treated as an activity of hardware optimization. A great deal of the effort in this area is concentrated on component activation, deactivation, and resource scheduling in order to provide a reduction of total power consumption. This work focuses on the study of power consumption from the developer's point of view, using a reliable power measurement framework to validate the literature's premise that programming options, such as multiplication operations, are high consumers of power energy. Besides some elementary operations and authors' suggestions about alternatives for power consumption reduction on the programming stage, we also compare and evaluate two well-known and widely applied algorithms for large number multiplication: Karatsuba and Toom-Cook. The obtained results provide guidelines to the developer in the programming phase to choose, in some cases, the best technique to reduce power consumption, speed up the software, and establish a maximum power limit for the completed software.

关键词： arithmetic algorithms power consumption power measurement framework

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Digital arithmetic in Nature: Continuous-Digit RNS

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COMPUTER JOURNAL 2015年第5期58卷 1214-1223页

作者： Parhami, Behrooz Univ Calif Santa Barbara Santa Barbara CA 93106 USA

It has been reported in the literature on computational neuroscience that a rat's uncanny ability to dash back to a home position in the absence of any visual clues (or in total darkness, for that matter) may stem from its distinctive method of position representation. More specifically, it is hypothesized that the rat uses a multimodular method akin to residue number system (RNS), but with continuous residues or digits, to encode position information. After a brief review of the evidence in support of this hypothesis, and how it relates to RNS, we discuss the properties of continuous-digit RNS, and derive results on the dynamic range, representational accuracy and factors affecting the choice of the moduli, which are themselves real numbers. We conclude with suggestions for further research on important open problems concerning the process of selection, or evolutionary refinement, of the set of moduli in such a representation.

关键词： arithmetic algorithms continuous-valued digits hybrid analog/digital encoding number representation

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A Hardware Implementation of arithmetic Operations for an FPGA-based Programmable Logic Controller 13

A Hardware Implementation of Arithmetic Operations for an FP...

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13th IFAC and IEEE Conference on Programmable Devices and Embedded Systems

作者： Kulisz, Jozef Chmiel, Miroslaw Krzyzyk, Adrian Rosol, Marcin Silesian Tech Univ Inst Elect Gliwice Poland

The paper presents the arithmetic and Logic Unit (ALU) of a prototype Programmable Logic Controller (PLC), implemented in an FPGA device. The PLC implements on the machine language level a subset of the instruction set defined in the EN 61131-3 norm. The design was prepared as a set of synthesizable Verilog. and VHDL models. The ALU can execute 32 operations, which include the basic logic operations, comparators. and the four basic arithmetic operations. The operations can be performed for fixed-point, and floating-point numbers. All the operations are implemented fully in hardware, so the solution is fast. The HDL models used for synthesis can be easily ported to other FPGA architectures, or to an ASIC. (C) 2015, IFAC (International Federation of Automatic Control) Hosting by Elsevier Ltd. All rights reserved.

关键词： Programmable logic controllers Central processing units arithmetic and logic units arithmetic algorithms Microprocessors Digital circuits Logic arrays Field programmable gate arrays Floating-point arithmetic

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A close encounter with Random Numbers 3

A close encounter with Random Numbers

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3rd International Conference on Computer, Communication, Control and Information Technology (C3IT)

作者： Das, Subrata Dasgupta, Parthasarathi Pandey, Amit Roy, Pabitra Acad Technol Dept Informat Technol Hooghly India Indian Inst Management Calcutta MIS Grp Kolkata India Univ Calcutta Dept Comp Sci & Engn Kolkata India

ISBN: (纸本)9781479944453

Performance profiling or empirical testing, and statistical testing of algorithms for NP-complete problems is typically based on random sample testing. Random values constitute a good source of data for testing the effectiveness of a computer algorithm. Random number generation is an absolute proposition. As such, generally the concentration is on realistic pseudorandom number generation. There are numerous pseudorandom number generation algorithms. We propose here another drop in the sea which is at least as efficient as the existing algorithms and simpler in certain respects.

关键词： algorithms arithmetic algorithms random number pseudorandom number

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Posibits, Negabits, and Their Mixed Use in Efficient Realization of arithmetic algorithms

Posibits, Negabits, and Their Mixed Use in Efficient Realiza...

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15th CSI International Symposium on Computer Architecture and Digital Systems (CADS)

作者： Jaberipur, G. Parhami, B. Shahid Beheshti Univ Dept Elect & Comp Engn Tehran Iran Sch Comp Sci Inst Res Fundamental Sci IPM Tehran Iran Univ Calif Santa Barbara Dept Elect & Comp Engn Santa Barbara CA 93106 USA

ISBN: (纸本)9781424462698

Positively weighted and negatively weighted bits (posibits, negabits) have been used in the interpretation of 2's-complement, negative-radix, and binary signed-digit number representation schemes as a way of facilitating the development of efficient arithmetic algorithms for various application domains. In this paper, we show that a more general view of posibits and negabits, along with their mixed use in any combination (using inverse encoding for negabits), unifies a number of diverse implementation schemes, while at the same time making the resultant designs more efficient by avoiding custom or modified hardware elements and restricting the implementation to the use of standard arithmetic cells. Such standard cells have been highly optimized and are continually improving due to their wide applicability. Other practical benefits of our formulation include facilitation of low-voltage and low-power design, again due to the widespread availability of standard cells in variants optimized for low-voltage operation or energy economy. Pedagogical benefits include more intuitive explanations for a number of widely used transformations, such as Booth's recoding and column compression.

关键词： Booths recoding arithmetic algorithms arithmetic codes binary signed digit number representation diverse implementation efficient arithmetic algorithms efficient realization energy economy low voltage operation modified hardware elements negatively weighted bits pedagogical benefits positively weighted bits residue number systems standard arithmetic cells

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