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AxOMaP: designing FPGA-based Approximate arithmetic operators using Mathematical Programming

ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS 2024年第2期17卷 1-28页

作者： Sahoo, Siva Satyendra Ullah, Salim Kumar, Akash Imec 1 Interunivers Microelect Ctr IMEC Kapeldreef 75 B-3001 Leuven Belgium Tech Univ Dresden Chair Processor Design Cfaed D-01062 Dresden Germany

With the increasing application of machine learning (ML) algorithms in embedded systems, there is a rising necessity to design low-cost computer arithmetic for these resource-constrained systems. As a result, emerging models of computation, such as approximate and stochastic computing, that leverage the inherent error-resilience of such algorithms are being actively explored for implementing ML inference on resourceconstrained systems. Approximate computing (AxC) aims to provide disproportionate gains in the power, performance, and area (PPA) of an application by allowing some level of reduction in its behavioral accuracy (BEHAV). Using approximate operators (AxOs) for computer arithmetic forms one of the more prevalent methods of implementing AxC. AxOs provide the additional scope for finer granularity of optimization, compared to only precision scaling of computer arithmetic. To this end, the design of platform-specific and cost-efficient approximate operators forms an important research goal. Recently, multiple works have reported the use of AI/ML-based approaches for synthesizing novel FPGA-based AxOs. However, most of such works limit the use of AI/ML to designing ML-based surrogate functions that are used during iterative optimization processes. To this end, we propose a novel data analysis-driven mathematical programming-based approach to synthesizing approximate operators for FPGAs. Specifically, we formulate mixed integer quadratically constrained programs based on the results of correlation analysis of the characterization data and use the solutions to enable a more directed search approach for evolutionary optimization algorithms. Compared to traditional evolutionary algorithms-based optimization, we report up to 21% improvement in the hypervolume, for joint optimization of PPA and BEHAV, in the design of signed 8-bit multipliers. Further, we report up to 27% better hypervolume than other state-of-the-art approaches to DSE for FPGA-based application-speci

关键词： Approximate computing arithmetic operator design circuit synthesis AI-based exploration

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AxOCS: Scaling FPGA-Based Approximate operators Using Configuration Supersampling

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2024年第6期71卷 2646-2659页

作者： Sahoo, Siva Satyendra Ullah, Salim Bhattacharjee, Soumyo Kumar, Akash IMEC B-3001 Leuven Belgium Ruhr Univ Bochum Chair Embedded Syst D-44801 Bochum Germany Swiss Fed Inst Technol Dept Informat Technol & Elect Engn ITET CH-8006 Zurich Switzerland

The rising usage of AI/ML-based processing across application domains has exacerbated the need for low-cost ML implementation, specifically for resource-constrained embedded systems. To this end, approximate computing, an approach that explores the power, performance, area (PPA), and behavioral accuracy (BEHAV) trade-offs, has emerged as a possible solution for implementing embedded machine learning. Due to the predominance of MAC operations in ML, designing platform-specific approximate arithmetic operators forms one of the major research problems in approximate computing. Recently, there has been a rising usage of AI/ML-based design space exploration techniques for implementing approximate operators. However, most of these approaches are limited to using ML-based surrogate functions for predicting the PPA and BEHAV impact of a set of related design decisions. While this approach leverages the regression capabilities of ML methods, it does not exploit the more advanced approaches in ML. To this end, we propose, a methodology for designing approximate arithmetic operators through ML-based supersampling. Specifically, we present a method to leverage the correlation of PPA and BEHAV metrics across operators of varying bit-widths for generating larger bit-width operators. The proposed approach involves traversing the relatively smaller design space of smaller bit-width operators and employing its associated design-PPA-BEHAV relationship to generate initial solutions for metaheuristics-based optimization for larger operators. The experimental evaluation of for FPGA-optimized approximate operators shows that the proposed approach significantly improves the quality-resulting hypervolume for multi-objective optimization-of 8 x 8 signed approximate multipliers.

关键词： AI-based design space exploration approximate computing arithmetic operator design circuit synthesis

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AxOTreeS: A Tree Search Approach to Synthesizing FPGA-based Approximate operators

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ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS 2023年第5期22卷 1-26页

作者： Sahoo, Siva Satyendra Ullah, Salim Kumar, Akash Interuniv Microelect Ctr IMEC 1 Kapeldreef 75 B-3001 Leuven Belgium Tech Univ Dresden Cfaed Dresden Germany Barkhausen Bau Flugel D Georg Schumann Str 11 D-01069 Dresden Germany

Approximate computing (AxC) provides the scope for achieving disproportionate gains in a system's power, performance, and area (PPA) metrics by leveraging an application's inherent error-resilient behavior (BEHAV). Trading computational accuracy for performance gains makes AxC an attractive proposition for implementing computationally complex AI/ML-based applications on resource-constrained embedded systems. The growing diversity of application domains using AI/ML has also led to the increasing usage of FPGA-based embedded systems. However, implementing AxC for FPGAs has primarily been limited to the post-processing of ASIC-optimized approximate operators (AxOs). This approach usually involves selecting from a set of AxOs that have been optimized for a gate-based implementation in an ASIC. While such an approach does allow leveraging existing knowledge of ASIC-based AxO design, it limits the scope for considering the challenges and opportunities associated with FPGA's LUT-based computation structures. Similarly, the few works considering the LUT-based computing for AxO design use generic optimization approaches that do not allow integrating problem-specific prior knowledge-empirical and/or statistical. To this end, we propose a novel tree search-based approach to AxO synthesis for FPGAs. Specifically, we present a design methodology using Monte Carlo Tree Search (MCTS)-based search tree traversal that allows the designer to integrate statistical data, such as correlation, into the AxOs optimization. With the proposed methods, we report improvements over standard MCTS algorithm-based results as well as improved hypervolume for both operator-level and application-specific DSE, compared to state-of-the-art design methodologies.

关键词： Approximate computing arithmetic operator design circuit synthesis AI-based exploration computer arithmetic automated hardware design Monte Carlo Tree Search

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SyFAxO-GeN: Synthesizing FPGA-based Approximate operators with Generative Networks 23

SyFAxO-GeN: Synthesizing FPGA-based Approximate Operators wi...

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28th Asia and South Pacific design Automation Conference (ASP-DAC)

作者： Ranjan, Rohit Ullah, Salim Sahoo, Siva Satyendra Kumar, Akash Tech Univ Dresden Dresden Ctr Adv Elect Dresden cfaed Chair Processor Design Dresden Germany

ISBN: (纸本)9781450397834

With rising trends of moving AI inference to the edge, due to communication and privacy challenges, there has been a growing focus on designing low-cost Edge-AI. Given the diversity of application areas at the edge, FPGA-based systems are increasingly used for high-performance inference. Similarly, approximate computing has emerged as a viable approach to achieve disproportionate resource gains by utilizing the applications' inherent robustness. However, most related research has focused on selecting the appropriate approximate operators for an application from a set of ASIC-based designs. This approach fails to leverage the FPGA's architectural benefits and limits the scope of approximation to already existing generic designs. To this end, we propose an AI-based approach to synthesizing novel approximate operators for FPGA's Look-uptable-based structure. Specifically, we use state-of-the-art generative networks to search for constraint-aware arithmetic operator designs optimized for FPGA-based implementation. With the proposed GANs, we report up to 49% faster training, with negligible accuracy degradation, than related generative networks. Similarly, we report improved hypervolume and increased pareto-front design points compared to state-of-the-art approaches to synthesizing approximate multipliers.

关键词： Approximate Computing arithmetic operator design Circuit Synthesis AI-based Exploration

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CoOAx: Correlation-aware Synthesis of FPGA-based Approximate operators 23

CoOAx: Correlation-aware Synthesis of FPGA-based Approximate...

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33rd Great Lakes Symposium on VLSI (GLSVLSI)

作者： Ullah, Salim Sahoo, Siva Satyendra Kumar, Akash Tech Univ Dresden Processor Design Cfaed Dresden Germany

ISBN: (纸本)9798400701252

The run-time reconfigurability and high parallelism offered by FP-GAs make them an attractive choice for implementing hardware accelerators for ML algorithms. In the quest for designing efficient FPGA-based hardware accelerators for ML algorithms, the inherent error-resilience of ML algorithms can be exploited to implement approximate hardware accelerators to trade the output accuracy with better overall performance. As multiplication and addition are the two main arithmetic operations in ML algorithms, most state-of-the-art approximate accelerators have considered approximate architectures for these operations. However, these works have mainly considered the exploration and selection of approximate operators from an existing set of operators. To this end, we provide an efficient methodology for synthesizing and implementing novel approximate operators. Specifically, we propose a novel operator synthesis approach that supports multiple operator algorithms to provide new approximate multiplier and adder designs for AI inference applications. We report up to 27% and 25% lower power than state-of-the-art approximate designs, with equivalent error behavior, for 8-bit unsigned adders and 4-bit signed multipliers respectively. Further, we propose a correlation-aware design space exploration method that can improve the efficacy of randomized search algorithms in synthesizing novel approximate operators.

关键词： Approximate Computing arithmetic operator design Circuit Synthesis AI-based Exploration

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PosAx-O: Exploring operator-level Approximations for Posit arithmetic in Embedded AI/ML 25

PosAx-O: Exploring Operator-level Approximations for Posit A...

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25th Euromicro Conference on Digital System design (DSD)

作者： Immaneni, Amritha Ullah, Salim Nambi, Suresh Sahoo, Siva Satyendra Kumar, Akash Tech Univ Dresden Chair Processor Design Ctr Adv Elect Dresden Cfaed Dresden Germany

ISBN: (纸本)9781665474047

The quest for low-cost embedded AI/ML applications has motivated innovations across multiple abstractions of the computation stack. Novel approaches for arithmetic operations have primarily involved quantization, precision-scaling, approximations, and modified data representation. In this context, Posit has emerged as an alternative to the IEEE-754 standard as it offers multiple benefits, primarily due to its dynamic range and tapered precision. However, the implementation of Posit arithmetic operations tends to result in high resource utilization and power dissipation. Consequently, recent works have delved into the idea of exploiting the error resilience of machine learning algorithms by using low-precision Posit arithmetic. However, limiting the exploration to precision-scaling limits the scope for application-specific optimizations for embedded AI/ML applications. To this end, we explore operator-level optimizations and approximations for low-precision Posit numbers. Specifically, we identify and eliminate redundant operations in state-of-the-art Posit arithmetic operator designs and provide a modular framework for exploring approximations in various stages of the computation. We also present a novel framework for behaviorally testing the corresponding Posit approximate designs in Artificial Neural Networks. The proposed optimizations and approximations exhibit considerable resource improvements with a small error in many cases. For instance, a Posit-based multiplier with 1-bit reduced precision shows a 33% improvement in power and utilization, with only a 0.2% degradation in overall accuracy.

关键词： Approximate Computing arithmetic operator design Circuit Synthesis Posit arithmetic

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