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2nd International Symposium of Electronics Design Automation (ISEDA)

作者： Hou, Renjing Zhai, Jianwang Wang, Yajun Lin, Zhe Zhao, Kang Beijing Univ Posts & Telecommun Sch Integrated Circuits Beijing Peoples R China Tiangong Univ Sch Elect & Informat Engn Tianjin Peoples R China Sun Yat Sen Univ Sch Integrated Circuits Guangzhou Guangdong Peoples R China

ISBN: (纸本)9798350352047;9798350352030

High-level synthesis (HLS) is a popular method that allows designers to describe the behavior-level functionality and automatically generates efficient register-transfer level (RTL) descriptions. In HLS, dataflow is the key micro-architecture to achieve high parallelism. However, strict conditions such as sequential access on the potential channels often limit the streaming dataflow. To settle this issue, this paper proposes an efficient array partitioning method for the streaming dataflow inference. The key is to explore the potential array partitioning mode that matches the sequential access requirements by streaming channels. An experimental case study is presented on the inference of the convolutional neural networks (CNN). It indicates that the proposed method can achieve about 28.6% performance improvements compared with the default dataflow, with the cost of 7.2% power increasement.

关键词： High-level Synthesis Streaming Dataflow array partitioning FPGA

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Scalable Near-Field Localization Based on array partitioning and Angle-of-Arrival Fusion 59

Scalable Near-Field Localization Based on Array Partitioning...

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59th Annual IEEE International Conference on Communications (IEEE ICC)

作者： Zheng, Yuqing Zhang, Mingchen Teng, Boyu Yuan, Xiaojun Univ Elect Sci & Tech China Natl Key Lab Wireless Commun Chengdu Peoples R China

ISBN: (纸本)9781728190549

Existing near-field localization algorithms generally face a scalability issue when the number of antennas at the sensor array goes large. To address this issue, this paper studies a passive localization system, where an extremely large-scale antenna array (ELAA) is deployed at the base station (BS) to locate a user that transmits signals. The user is considered to be in the near-field (Fresnel) region of the BS array. We propose a novel algorithm, named array partitioning based location estimation (APLE), for scalable near-field localization. The APLE algorithm is developed based on the basic assumption that, by partitioning the ELAA into multiple subarrays, the user can be approximated as in the far-field region of each subarray. The APLE algorithm determines the user's location by exploiting the differences in the angles of arrival (AoAs) of the subarrays. Specifically, we establish a probability model of the received signal based on the geometric constraints of the user's location and the observed AoAs. Then, a message-passing algorithm, i.e., the proposed APLE algorithm, is designed for user localization. APLE exhibits linear computational complexity with the number of BS antennas, leading to a significant reduction in complexity compared to the existing methods. Besides, numerical results demonstrate that the proposed APLE algorithm outperforms the existing baselines in terms of localization accuracy.

关键词： Near-field localization extremely large-scale antenna array array partitioning Bayesian inference

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Efficient partitioning Method for Optimizing the Compression on array Data

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Journal of Computer Science & Technology 2022年第5期37卷 1049-1067页

作者： Shuai Han Xian-Min Liu Jian-Zhong Li Faculty of Computing Harbin Institute of TechnologyHarbin 150001China

array partitioning is an important research problem in array management area,since the partitioning strategies have important influence on storage,query evaluation,and other components in array management ***,compression is highly needed for the array data due to its growing *** that the array partitioning can affect the compression performance significantly,this paper aims to design the efficient partitioning method for array data to optimize the compression *** far as we know,there still lacks research efforts on this *** this paper,the problem of array partitioning for optimizing the compression performance(PPCP for short)is firstly *** adopt a popular compression technique which allows to process queries on the compressed data without ***,because the above problem is NP-hard,two essential principles for exploring the partitioning solution are introduced,which can explain the core idea of the partitioning algorithms proposed by *** first principle shows that the compression performance can be improved if an array can be partitioned into two parts with different *** second principle introduces a greedy strategy which can well support the selection of the partitioning positions *** by the two principles,two greedy strategy based array partitioning algorithms are designed for the independent case and the dependent case *** the expensive cost of the algorithm for the dependent case,a further optimization based on random sampling and dimension grouping is proposed to achieve linear time ***,the experiments are conducted on both synthetic and real-life data,and the results show that the two proposed partitioning algorithms achieve better performance on both compression and query evaluation.

关键词： array partitioning compression performance greedy strategy NP-hard

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Scalable Near-Field Localization Based on Partitioned Large-Scale Antenna array

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IEEE TRANSACTIONS ON WIRELESS COMMUNICATIONS 2025年第3期24卷 2203-2217页

作者： Yuan, Xiaojun Zhang, Mingchen Zheng, Yuqing Teng, Boyu Jiang, Wenjun Univ Elect Sci & Technol China Yangtze Delta Reg Inst Huzhou Huzhou 313001 Peoples R China Univ Elect Sci & Technol China Natl Key Lab Wireless Commun Chengdu 611731 Peoples R China Univ Elect Sci & Technol China Natl Key Lab Wireless Commun Chengdu 611731 Peoples R China

This paper studies a localization system, where an extremely large-scale antenna array (ELAA) is deployed at the base station (BS) to locate a user equipment (UE) residing in the near-field (Fresnel) region. We propose a novel algorithm, named array partitioning-based location estimation (APLE), for scalable near-field localization. The APLE algorithm is developed based on the basic assumption that, by partitioning the ELAA into multiple subarrays, the UE can be approximated as in the far-field region of each subarray. We establish a Bayeian inference framework based on the geometric constraints between the UE location and the angles of arrivals (AoAs) at different subarrays. Then, the APLE algorithm is designed based on the message-passing principle for the localization of the UE. APLE exhibits linear computational complexity with the number of BS antennas, leading to a significant reduction in complexity compared to existing methods. We further propose an enhanced APLE (E-APLE) algorithm that refines the location estimate obtained from APLE by following the maximum likelihood principle. The E-APLE algorithm achieves superior localization accuracy compared to APLE while maintaining a linear complexity with the number of BS antennas. Numerical results demonstrate that the proposed APLE and E-APLE algorithms outperform the existing baselines in terms of both localization accuracy and computational complexity.

关键词： Near-field localization extremely large-scale antenna array array partitioning array partitioning Bayesian inference Bayesian inference Bayesian inference

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DYNAMIC partitioning FOR array LANGUAGES

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COMMUNICATIONS OF THE ACM 1972年第12期15卷 1023-&页

作者： PHILLIPS, JR ADAMS, HC Univ. of Illinois at Urbana-Champaign Urbana Eglin Air Force Base FL

The classical process of partitioning an array into subarrays is extended to a more useful array language operation. Various modes of partitioning are defined for different types of arrays, so that subarrays may vary over the original array in a nearly arbitrary manner. These definitions are motivated with several realistic examples to illustrate the value of partitioning for array languages. Of general interest Is the data structure for partitioning. This consists of dynamic tree structures which are used to derive and maintain the array control information. These are described in sufficient detail to be of value In the design of other array languages. The description presented in this paper is Implemented in a new array language, OL/2, currently under development at the University of lllinois. [ABSTRACT FROM AUTHOR]

关键词： array control blocks array language array partitioning data structure dynamic partitioning partition control blocks programming language design tree structure

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A high-speed reusable quantized hardware accelerator design for CNN on constrained edge device

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DESIGN AUTOMATION FOR EMBEDDED SYSTEMS 2023年第3期27卷 165-189页

作者： Yanamala, Rama Muni Reddy Pullakandam, Muralidhar Natl Inst Technol Warangal Elect & Commun Engn Warangal 506004 Telangana India

The most recent deep learning technique used in many applications is the convolutional neural network (CNN). Recent years have seen a rise in demand for real-time CNN implementations on various embedded devices with restricted resources. The CNN models should be implemented using field-programmable gate arrays to ensure flexible programmability and speed up the development process. However, the CNN acceleration is hampered by complex computations, limited bandwidth, and on-chip memory storage. In this paper, a reusable quantized hardware architecture was proposed to accelerate deep CNN models by solving the above issues. Twenty-five processing elements are employed for the computation of convolutions in the CNN model. Pipelining, loop unrolling, and array partitioning are the techniques for increasing the speed of computations in both the convolution layers and fully connected layers. This design is tested with MNIST handwritten digit image classification on a low-cost, low-memory Xilinx PYNQ-Z2 system on chip edge device. The inference speed of the proposed hardware design achieved 92.7% higher than INTEL core3 CPU, 90.7% more than Haswell core2 CPU, 87.7% more than NVIDIA Tesla K80 GPU, and 84.9% better when compared to the conventional hardware accelerator with one processing element. The proposed quantized architecture design has achieved the performance of 4.4 GOP/s without compromising the accuracy and it was 2 times more than the conventional architecture.

关键词： Convolutional neural network (CNN) array partitioning Processing element Field-programmable gate array (FPGA) platform PYNQ-Z2 On-chip data storage

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An OpenMP Compiler for Efficient Use of Distributed Scratchpad Memory in MPSoCs

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IEEE TRANSACTIONS ON COMPUTERS 2012年第2期61卷 222-236页

作者： Marongiu, Andrea Benini, Luca Univ Bologna DEIS I-40136 Bologna Italy

Most of today's state-of-the-art processors for mobile and embedded systems feature on-chip scratchpad memories. To efficiently exploit the advantages of low-latency high-bandwidth memory modules in the hierarchy, there is the need for programming models and/or language features that expose such architectural details. On the other hand, effectively exploiting the limited on-chip memory space requires the programmer to devise an efficient partitioning and distributed placement of shared data at the application level. In this paper, we propose a programming framework that combines the ease of use of OpenMP with simple, yet powerful, language extensions to trigger array data partitioning. Our compiler exploits profiled information on array access count to automatically generate data allocation schemes optimized for locality of references.

关键词： MPSoC OpenMP array partitioning multiple scratchpads NUMA

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3D Localization With a Single Partially-Connected Receiving RIS: Positioning Error Analysis and Algorithmic Design

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IEEE TRANSACTIONS ON VEHICULAR TECHNOLOGY 2023年第10期72卷 13190-13202页

作者： He, Jiguang Fakhreddine, Aymen Vanwynsberghe, Charles Wymeersch, Henk Alexandropoulos, George C. Technol Innovat Inst Abu Dhabi 9639 U Arab Emirates Chalmers Univ Technol Dept Elect Engn S-41258 Gothenburg Sweden Natl & Kapodistrian Univ Athens Dept Informat & Telecommun Athens 15784 Greece

In this article, we introduce the concept of partially-connected receiving reconfigurable intelligent surfaces (R-RISs), which refers to metasurfaces designed to efficiently sense electro-magnetic waveforms impinging on them, and perform localization of the users emitting them. The presented R-RIS hardware architecture comprises subarrays of meta-atoms, with each of them incorporating a waveguide assigned to direct the waveforms reaching itsmeta-atoms to a reception radio-frequency (RF) chain, enabling signal/channel parameter estimation. We particularly focus on the scenarios where the user is located in the far-field of all the R-RIS subarrays, and present a three-dimensional (3D) localization method which is based on narrowband signaling and angle of arrival (AoA) estimates of the impinging signals at each single-receive-RF R-RIS subarray. For the AoA estimation, which relies on spatially sampled versions of the received signals via each subarray's phase configuration of meta-atoms, we devise an off-grid atomic norm minimization approach, which is followed by subspace-based root multiple signal classification (MUSIC). The AoA estimates are finally combined via a least-squared line intersection method to obtain the position coordinates of a user emitting synchronized localization pilots. Our derived theoretical Cramer Rao lower bounds (CRLBs) on the estimation parameters, which are compared with extensive computer simulation results of our localization approach, verify the effectiveness of the proposed R-RIS-empowered 3D localization system, which is showcased to offer cm-level positioning accuracy. Our comprehensive performance evaluations also demonstrate the impact of various system parameters on the localization performance, namely the training overhead and the distance between the R-RIS and the user, as well as the spacing among the R-RIS's subarrays and its partitioning patterns.

关键词： 3D localization array partitioning atomic norm minimization Cramer Rao lower bound direction estimation MUSIC reconfigurable intelligent surface

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COMPUTING TRANSITIVE CLOSURE ON SYSTOLIC arrayS OF FIXED SIZE

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DISTRIBUTED COMPUTING 1991年第3期5卷 133-144页

作者： LISPER, B ROYAL INST TECHNOL S-10044 STOCKHOLM 70SWEDEN

Forming the transitive closure of a binary relation (or directed graph) is an important part of many algorithms. When the relation is represented by a bit matrix, the transitive closure can be efficiently computed in parallel in a systolic array. Here we propose two novel ways of computing the transitive closure of an arbitrarily big graph on a systolic array of fixed size. The first method is a simple partitioning of a well-known systolic algorithm for computing the transitive closure. The second is a block-structured algorithm. This algorithm is suitable for execution on a systolic array that can multiply fixed size bit matrices and compute transitive closure of graphs with a fixed number of nodes. The algorithm is, however, not limited to systolic array implementations;it works on any parallel architecture that can perform these bit matrix operations efficiently. The shortest path problem, for directed graphs with weighted edges, can also be solved in the same manner, devised above, as the transitive closure is computed.

关键词： SYSTOLIC array TRANSITIVE CLOSURE SHORTEST PATH VLSI ALGORITHM array partitioning PARALLEL ALGORITHM

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Memory Optimization for Accelerating Hough Transform on FPGA using High Level Synthesis 4

Memory Optimization for Accelerating Hough Transform on FPGA...

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4th IEEE International Circuits and Systems Symposium (ICSyS)

作者： Solod, Panadda Jindapetch, Nattha Sengchuai, Kiattisak Booranawong, Apidet Hoyingcharoen, Pakpoom Chumpol, Surachate Ikura, Masami Prince Songkla Univ Songkhla Dept Elect Engn Hat Yai Thailand Toyota Tsusho Nexty Elect Thailand Co Ltd Bangkok Thailand

ISBN: (纸本)9781728100241

In this work, we present memory optimization in Hough transform on hardware of programmable logic (PL) part of FPGAs by using array partitioning block, cyclic and complete types at different dimension and different factor on the Xilinx Vivado High Level Synthesis tool. Loop analysis was presented to extract nested loops and suitably manage the array. The experimental results show that adding array partitioning complete type at dimension 2 can be the best type to improve speed of operating time and reduce the number of resources on Zybo ZC7010-1.

关键词： array partitioning High Level Synthesis (HLS) FPGA Hough transform

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