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Design of a clustered data-driven array processor for computer vision

High Technology Letters 2020年第4期26卷 424-434页

作者： Shan Rui Deng Junyong Jiang Lin Zhu Yun Wu Haoyue He Feilong School of Electronic and Engineering Xi’an University of Posts and TelecommunicationsXi’an 710121P.R.China Integrated Circuit Laboratory Xi’an University of Science and TechnologyXi’an 710054P.R.China

Computer vision(CV)is widely expected to be the next big thing in emerging *** many heterogeneous architectures for computer vision ***,plenty of data need to be transferred between different structures for heterogeneous *** long data transfer delay becomes the mainly problem to limit the processing speed for computer vision *** reducing data transfer delay and fasting computer vision applications,a clustered data-driven array processor is proposed.A three-level pipelining processing element is designed which supports two-buffer data flow interface and 8 bits,16 bits,32 bits subtext parallel *** the same time,for accelerating transcendental function computation,a four-way shared pipelining transcendental function accelerator is designed,which is based on Y-intercept adjusted piecewise linear segment algorithm.A distributed shared memory structure based on unified addressing is also *** verify efficiency of architecture,some image processing algorithms are implemented on proposed *** the proposed architecture has been implemented on Xilinx ZC 706 development *** same circuitry has been synthesized using SMIC 130 nm CMOS *** circuitry is able to run at 100 *** is 26.58 mm2.

关键词： array processor data-driven adjacent interconnection distributed memory computer vision(CV)

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ACCESS AND ALIGNMENT OF DATA IN AN array processor

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IEEE TRANSACTIONS ON COMPUTERS 1975年第12期24卷 1145-1155页

作者： LAWRIE, DH UNIV ILLINOIS DEPT COMP SCIURBANAIL 61801

This paper discusses the design of a primary memory system for an array processor which allows parallel, conflict-free access to various slices of data (e.g., rows, columns, diagonals, etc.), and subsequent alignment of these data for processing. Memory access requirements for an array processor are discussed in general terms and a set of common requirements are defined. The ability to meet these requirements is shown to depend on the number of independent memory units and on the mapping of the data in these memories. Next, the need to align these data for processing is demonstrated and various alignment requirements are defined. Hardware which can perform this alignment function is discussed, e.g., permutation, indexing, switching or sorting networks, and a network (the omega network) based on Stone"s shuffle-exchange operation [1] is presented. Construction of this network is described and many of its useful properties are proven. Finally, as an example of these ideas, an array processor is shown which allows conflict-free access and alignment of rows, columns, diagonals, backward diagonals, and square blocks in row or column major order, as well as certain other special operations.

关键词： Alignment network array processor array storage conflict-free acess data alignment indexing network omega network parallel processing permutation network shuffle-exchange network storage mapping switching network.

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APPLICATION OF AN array processor TO IMAGE-PROCESSING IN ELECTRON-MICROSCOPY

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JOURNAL OF MICROSCOPY-OXFORD 1982年第JUL期127卷 85-91页

作者： PITT, TJ European Molecular Biology Laboratory Postfach 10.2209 D6900 Heidelberg West Germany

It is now possible to obtain a number of so-called array processors to attach to existing computer systems, to increase the computing power and speed available. In this paper, the application of one such array processor to image processing in electron microscopy is considered, and some of the practical experience thus gained is reported.

关键词： Image processing array processor

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BERKELEY array processor

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IEEE TRANSACTIONS ON COMPUTERS 1970年第5期C 19卷 444-&页

作者： DERE, WY SAKRISON, DJ IEEE

The Berkeley array processor is a special-purpose computer designed to perform the operations of correlation, convolution, recursive filtering, matrix multiplication, as well as a variant of the Cooley-Tukey algorithm... 详细信息

关键词： array processor convolution Cooley-Tukey algorithm correlation digital filtering Fourier transform special- purpose computer time series analysis.

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IMAGE-RECONSTRUCTION ON A SPECIAL PURPOSE array processor

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IMAGE AND VISION COMPUTING 1992年第7期10卷 479-484页

作者： KOUFOPAVLOU, OG GOUTIS, CE UNIV PATRAS DEPT ELECT ENGNMICROELECTR LABGR-26110 PATRASGREECE

High quality image reconstruction algorithms are of special importance for tomographic applications. This paper presents the register transfer level and the VLSI design of a special purpose array processor which realizes a tomographic algorithm having higher quality reconstructions than other well-known algorithms. The operation of the array processor is pipelined and, most important, the communication delays have been eliminated by overlapping arithmetic and logic operations with data transfer. The design and operation of the array processor, which fully exploits the special features of the algorithm to optimize the units and subunits, leads to high hardware utilization. In contrast to other attempts, the number of units is limited resulting in a reasonable sized hardware system achieving real-time reconstruction. The paper presents some important performance analysis of the proposed architecture.

关键词： IMAGE RECONSTRUCTION array processor

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FPGA Implementation of a SIMD-Based array processor with Torus Interconnect

FPGA Implementation of a SIMD-Based Array Processor with Tor...

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International Conference on Field Programmable Technology (FTP)

作者： Murakami, Yuki Univ Aizu Grad Sch Comp Sci & Engn Aizu Wakamatsu Fukushima Japan

ISBN: (纸本)9781467390910

Matrix computations are a fundamental tool in scientific and engineering applications. Among many such applications, Convolutional Neural Networks (CNN) that can be effectively computed by matrix-matrix multiplications are being popular and an efficient implementation of CNN is highly important. In this study, we have designed an parallel processor for the matrix computations using torus interconnect topology, and we implemented Cannon's algorithm for matrix-matrix multiply-add. We have evaluated the scalability of the proposed processor on a reconfigurable FPGA platform. More precisely, the designed processor with 8 x 8 functional units with 16 bit floating-point multiply-add unit was evaluated on Cyclone IV FPGA chip, with performance of 27 GFlops. We also implemented CNN calculations on our processor. We compared the matrix based approach and our proposed method. As a result, our method is 25 times faster than the matrix based approach if the processor has 8x8 functional units, image size is 32x32 and filter size is 5 x 5.

关键词： Matrix-Matrix Multiply-Add Convolution Convolutional Neural Networks array processor

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A special purpose array processor architecture for the molecular dynamics simulation of point-mutated proteins

A special purpose array processor architecture for the molec...

引用

12th IEEE Workshop on Neural Networks for Signal Processing

作者： Zimmermann, KH Tech Univ Hamburg Dept Comp Engn D-21071 Hamburg Germany

Point mutation of amino acids is a means used by biotechnologists to improve the performance of proteins. To study a point-mutated polypeptide, one requires its global minimum energy conformation. This conformation can be determined by molecular dynamics via Langevin's equations of motion. Molecular dynamics simulations belong to the most difficult problems to parallelize in a scalable manner. We provide a method for defining a special purpose 3D array processor architecture for the molecular dynamics simulation of point-mutated polypeptides. The architecture is derived from a spatial decomposition of a known conformation of the point-mutated polypeptide or the native conformation of the given protein. By using an approximation scheme for the deterministic forces, the interprocessor communication can be kept local. The architecture affords a simple distributed load balancer and is scalable. The computational workload of the array processor architecture to perform molecular dynamics simulations under realistic conditions is addressed. An example architecture is given by point-mutated penicillin amidase.

关键词： protein point mutation molecular dynamics parallel processing array processor penicillin amidase

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A Reconfigurable Parallelization of Generative Adversarial Networks based on array processor

A Reconfigurable Parallelization of Generative Adversarial N...

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Asia-Pacific-Signal-and-Information-Processing-Association Annual Summit and Conference (APSIPA ASC)

作者： Xie, Xiaoyan Chai, Miaomiao Du, Zhuolin Yang, Kun Yin, Shaorun Xian Univ Posts & Telecommun Xian Peoples R China

ISBN: (纸本)9789881476890

Aiming at the intensive calculations of convolution and the invalid calculations caused by "zero" inserted of deconvolution in Generative Adversarial Network (GAN), which makes difficulties of accelerated by hardware. Through analyzing of network structure and calculation flows of GAN, a paralleling scheme of reconfiguration for convolution and deconvolution is proposed in this paper. Based on the Dynamic Programmable Reconfigurable array processor (DPRAP), on a 4x4 processing elements (PEs) array, the flexible switching of the two convolution modes are driven by a H-tree controlled reconfiguration mechanism. The proposed scheme is verified based on the DPRAP. The experimental results show that, compared with other FPGA schemes, the resource occupation can be reduced by up to 90% at a working frequency of 150MHz. Performance has been significantly improved.

关键词： Generative Adversarial Network Parallelization array processor Reconfigurable

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Univac :: 1100 :: Brochures :: U6827R1 Series 1100 array processor Subsystem Jun82

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2016年

Univac :: 1100 :: Brochures :: U6827R1 Series 1100 array processor Subsystem Jun82 by published by

关键词： aps apu array array processor brochures control unit data floating point fortran jun82 processing system processor processor control processor subsystem processor unit real coefficient scan vector series sperry sperry univac subsystem system u6827r1 univac vector

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Mapping Data-Flow Graph to Loop Engine on array processor

Mapping Data-Flow Graph to Loop Engine on Array Processor

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The Fourth International Conference on Parallel and Distributed Computing, Applications and Technologies

作者： Yong Dou Xicheng Lu National Laboratory for Parallel and Distributed Processing

This paper presents a novel architecture for array processor,called LEAP,which is a set of simple processing *** targeted programs are perfect innermost *** using the technique called if-conversion,the control dependence can be converted to data dependence to prediction *** an innermost loop can be represented by a data dependence graph,where the vertex supports the expression statements of high level languages. By mapping the data dependence graph to fixed PEs,each PE steps the loop iteration automatically and independently at the *** execution forms multiple pipelining *** simulation of four loops of LFK shows the effectiveness of the LEAP architecture,compared with traditional CISC and RISC architectures.

关键词： array processor chip multiprocessor pipeline chaining

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