The multiassociative processor (MAP) system is a hypothetical machine composed of eight control units (CU"s) and an arbitrary number of processing elements (PE"s). Each CU is allocated a subset of the identi...
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The multiassociative processor (MAP) system is a hypothetical machine composed of eight control units (CU"s) and an arbitrary number of processing elements (PE"s). Each CU is allocated a subset of the identical PE"s in order to process a single-instruction-stream-multiple-data-stream program. The eight CU"s must be able to access a common main memory system and transmit data to subsets of the PE"s over a shared data bus system. This paper discusses the analysis of these two components of the system where this analysis relies heavily on three simulation programs. The first program interprets assembly language programs for the hypothetical machine and the other two programs model the memory system and the data bus system. The interpreter is driven by both realistic array processor programs and synthetic programs designed specifically to test the components of the system.
An image can be represented by a two-dimensional array of "image points," which are sets of integers that each describe the color and intensity of a portion of the image. Image-processing operations require ...
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An image can be represented by a two-dimensional array of "image points," which are sets of integers that each describe the color and intensity of a portion of the image. Image-processing operations require that an image or partial image be stored in a memory system that permits access to sequences of image points along any row or column of this image array and/or to the image points within small rectangular areas of the array. This paper describes a number of memory systems that permit access to 1 × pq,pq × 1 and/or p × q subarrays of an image array, where p and q are design parameters.
This paper explores the possibility of using a large-scale array of microprocessors as a computational facility for the execution of massive numerical computations with a high degree of parallelism. By microprocessor ...
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This paper discusses the design of a primary memory system for an array processor which allows parallel, conflict-free access to various slices of data (e.g., rows, columns, diagonals, etc.), and subsequent alignment ...
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This paper discusses the design of a primary memory system for an array processor which allows parallel, conflict-free access to various slices of data (e.g., rows, columns, diagonals, etc.), and subsequent alignment of these data for processing. Memory access requirements for an array processor are discussed in general terms and a set of common requirements are defined. The ability to meet these requirements is shown to depend on the number of independent memory units and on the mapping of the data in these memories. Next, the need to align these data for processing is demonstrated and various alignment requirements are defined. Hardware which can perform this alignment function is discussed, e.g., permutation, indexing, switching or sorting networks, and a network (the omega network) based on Stone"s shuffle-exchange operation [1] is presented. Construction of this network is described and many of its useful properties are proven. Finally, as an example of these ideas, an array processor is shown which allows conflict-free access and alignment of rows, columns, diagonals, backward diagonals, and square blocks in row or column major order, as well as certain other special operations.
Memory has always been a major factor in determining the cost of a computer system. Many schemes have been proposed for reducing memory cost without degrading system performance or increasing system cost or complexity...
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Memory has always been a major factor in determining the cost of a computer system. Many schemes have been proposed for reducing memory cost without degrading system performance or increasing system cost or complexity significantly. This paper presents a particular data type that may have been used occasionally by programmers who have had to simulate floating-point hardware by software. This new data type is useful in large scientific problems and may be able to serve as a replacement for floating-point data type on special-purpose processors. Its hardware implementation on orthogonal and pipeline processors is discussed in detail and the implications of these implementations for a programming language (APL) (Iverson"s language) are examined.
The CORDIC iteration is applied to several Fourier transform algorithms. The number of operations is found as a function of transform method and radix representation. Using these representations, several hardware conf...
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The CORDIC iteration is applied to several Fourier transform algorithms. The number of operations is found as a function of transform method and radix representation. Using these representations, several hardware configurations are examined for cost, speed, and complexity tradeoffs. A new, especially attractive FFT computer architecture is presented as an example of the utility of this technique. Compensated and modified CORDIC algorithms are also developed.
The Berkeley array processor is a special-purpose computer designed to perform the operations of correlation, convolution, recursive filtering, matrix multiplication, as well as a variant of the Cooley-Tukey algorithm...
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The Berkeley array processor is a special-purpose computer designed to perform the operations of correlation, convolution, recursive filtering, matrix multiplication, as well as a variant of the Cooley-Tukey algorithm, and others. This note describes the logical organization and performance of this device.
LSI will have a profound effect on the design of computer systems ranging from evolutionary changes in implementation to revolutionary changes in basic architecture. This paper discusses a computer composed of an arra...
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