A formal approach for the transformation of computation intensive digital signal processing algorithms into suitable array processor architectures is presented. It covers the complete design flow from algorithmic spec...
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A formal approach for the transformation of computation intensive digital signal processing algorithms into suitable array processor architectures is presented. It covers the complete design flow from algorithmic specifications in a high-level programming language to architecture descriptions in a hardware description language. The transformation itself is divided into manageable design steps and implemented in the CAD-tool DECOMP which allows the exploration of different architectures in a short time. With the presented approach data independent algorithms can be mapped onto array processor architectures. To allow this, a known mapping methodology for arrayprocessor design is extended to handle inhomogeneous dependence graphs with nonregular data dependences. The implementation of the formal approach in the DECOMP is an important step towards design automation for massively parallel systems.
A new arrayprocessor architecture for two-dimensional (2D) FIR digital filters is developed. The processor has two processing rates for processing 2D signals in two directions. It processes the input signal using a r...
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A new arrayprocessor architecture for two-dimensional (2D) FIR digital filters is developed. The processor has two processing rates for processing 2D signals in two directions. It processes the input signal using a row-by-row scheme. Owing to its high speed (about 30 images per second), it can be used for real-time image processing.
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