Focuses on the effectiveness of embedded processor in driving television on-screen display. Generation of synchronization signal through timer peripheral; Transmission of data from pixel map stored in memory; Modifica...
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Focuses on the effectiveness of embedded processor in driving television on-screen display. Generation of synchronization signal through timer peripheral; Transmission of data from pixel map stored in memory; Modification of horizontal/vertical resolution.
Single processors may be sufficient for low performance applications that are typical of early microcontrollers, but an increasing number of applications require multiprocessors to meet their performance goals. Multip...
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Single processors may be sufficient for low performance applications that are typical of early microcontrollers, but an increasing number of applications require multiprocessors to meet their performance goals. Multiprocessor systems-on-chips require single-chip implementations to meet the application's size and power consumption requirements. Some complex applications may require programmability. The applications that systems-on-chips designs target exhibit a combination of constraints, which are balanced by adapting the system's architecture to the application's requirements.
The time-domain formation, in terms of unified nodal equations, of a magnetized cold plasma in three-dimensional space using the Bergeron method is described. The validity of this treatment is shown by simulations of ...
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The time-domain formation, in terms of unified nodal equations, of a magnetized cold plasma in three-dimensional space using the Bergeron method is described. The validity of this treatment is shown by simulations of both transverse propagation and longitudinal propagation. In the formulation of the characteristic equation in the time domain, the authors introduce variables corresponding to the first and second derivates of the electric polarization. Thus the iterative computation can be performed by using only the values obtained at the previous time step. This procedure very closely matches the architecture for high-speed computation in the vector processor of a supercomputer. This property can render practical the simulation of three-dimensional fields involving gyroelectric anisotropic media and expand the generality of the numerical vector analysis method in the time domain.
As we move toward the nano-world of tomorrow, the potential is *** hype artists with wild imaginations have suggested powerful, invisible, self-reproducingmachines that could run around fixing things inside our bodies...
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As we move toward the nano-world of tomorrow, the potential is *** hype artists with wild imaginations have suggested powerful, invisible, self-reproducingmachines that could run around fixing things inside our bodies or building complex structuresmolecule by molecule, the real impact will probably be much more subtle and far-reaching. We willlearn how to harness nature's own methods for self-assembly, and then apply these self-organizingprinciples to structure new types of devices, perhaps with metamaterials having unique *** are already stain-proof fabrics, brighter displays requiring less energy, and nanoslurriesthat can improve chemical mechanical planariza-tion. Flash memories may soon require less power tohold more charge longer by using nanocrystals for the floating gate.
A deconvolution technique is described which utilizes orthogonal polynomials (DOP) and handles inevitable noise in such a way that pixel time activity curves can be deconvolved. This solves the issue of quantitative a...
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A deconvolution technique is described which utilizes orthogonal polynomials (DOP) and handles inevitable noise in such a way that pixel time activity curves can be deconvolved. This solves the issue of quantitative analysis of serial scintigraphic data in a manner that preserves the high spatial resolution inherent in raw data. In the current work a complete mathematical description of the new deconvolution technique is presented. The DOP method is designed for use with an array processor and results in a set of linear response function (LRF) images. Techniques to calibrate the measuring devices and correct for distorted input functions in order to obtain the LRF images in absolute units are described. A simulation study compares the DOP method with the Fourier transform and the discrete deconvolution algorithm both with and without various noise levels. The impact on the convergence of the DOP algorithm of undesired blood activity simultaneously measured with the organ-target activity was simulated.
The design, operation, and capabilities of a workstation-communications-simulation software system (WCS) for interactive simulation of point-to-point digital communication links is described. The system is based on Fo...
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The design, operation, and capabilities of a workstation-communications-simulation software system (WCS) for interactive simulation of point-to-point digital communication links is described. The system is based on Fortran-77 and is hosted on an IBM PC/AT or compatible microcomputer. At the heart of the system is a single-board floating-point array processor that provide approximately three orders of magnitude increase in computational throughput over operations performed in the AT alone. A description is given of how a unique method of interfacing to a PC host allows considerable flexibility in partitioning a simulation problem for execution on an attached processor. The WCS system is a highly graphics-oriented system using the latest advances in interactive color workstation technology.
The design of a fault-tolerant rectangular array of processing elements (PE's) is presented, in which the reconfiguration is done by means of on-chip distributed logic, without the help of any external host. Spare...
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The design of a fault-tolerant rectangular array of processing elements (PE's) is presented, in which the reconfiguration is done by means of on-chip distributed logic, without the help of any external host. Spare PE's are included in every column of the array, and faulty PE's are bypassed within a column to facilitate reconfiguration in the presence of faults. Scan paths are used to enhance the testability of the array. PE's are tested locally using near-neighbor comparisons without the need of an external host. Because the interconnections between logical neighbors are short, the speed penalty for reconfiguration is very small. Any amount of redundancy can be incorporated in the array without changing the topology of the scheme or the design of the reconfiguration switches. The scheme is well suited for very large-area, high-density chips and wafer-scale integration (WSI). In order to demonstrate the capabilities of the scheme and evaluate its performance, an experimental chip consisting of a 6 x 4 array was designed, fabricated, and tested. Details of the design and the implementation of the chip are included in the paper. The scheme is also analyzed for yield and area utilization for a range of array sizes and PE survival probabilities.
A highly constrained iterative technique for the optimisation of non-periodic, (random and sparse) array geometries is presented. This approach involves establishing a set of array configurations which seek to minimis...
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A highly constrained iterative technique for the optimisation of non-periodic, (random and sparse) array geometries is presented. This approach involves establishing a set of array configurations which seek to minimise the peak sidelobe level of the array beampattern. The technique, harmonic array design, quickly produces a constrained set of near-optimal array solutions which can then be tried and tested. This is seen as an alternative to intensive computational search algorithms. Results of simulations for ten element linear non-periodic arrays are presented and their performance compared with equivalent periodic arrays. Such non-periodic arrays have the potential to offer improved angular resolution at a lower cost than periodic designs and have applications in all forms of acoustic and electromagnetic imaging. Here, the particular application of digital sonar beamforming is considered.
An improvement of the non-restoring array divider with carry-save and carry-look-ahead (CLA) techniques (by Cappa-Hamacher) is presented in this paper. Both the speed and gate counts for this array are enhanced. Becau...
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An improvement of the non-restoring array divider with carry-save and carry-look-ahead (CLA) techniques (by Cappa-Hamacher) is presented in this paper. Both the speed and gate counts for this array are enhanced. Because the number of types of basic cells is reduced from three to two, the homogeneity and modularity of the cellular structure are increased. The I/O pins of one basic cell are also reduced. All these properties are very attractive for VLSI implementation..
This paper presents a formal model of linear array processors suitable for VLSI implementation as well as graph representations of programs suitable for execution on such a model. A distinction is made between correct...
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This paper presents a formal model of linear array processors suitable for VLSI implementation as well as graph representations of programs suitable for execution on such a model. A distinction is made between correct mapping and correct execution of such graphs on this model and the structure of correctly mappable graphs are examined. The formalism developed is used to synthesize algorithms for this model.
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