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Design Space Exploration of Deeply Nested Loop 2D Filtering and 6 Level FSBM Algorithm Mapped onto Systolic array

VLSI DESIGN 2012年第unknown期2012卷 389-403页

作者： Sundari, B. Bala Tripura Amrita Vishwa Vidyapeetham Dept ECE Coimbatore 641112 Tamil Nadu India

The high integration density in today's VLSI chips offers enormous computing power to be utilized by the design of parallel computing hardware. The implementation of computationally intensive algorithms represented by n-dimensional (n-D) nested loop algorithms, onto parallel array architecture is termed as mapping. The methodologies adopted for mapping these algorithms onto parallel hardware often use heuristic search that requires a lot of computational effort to obtain near optimal solutions. We propose a new mapping procedure wherein a lower dimensional subspace (of the n-D problem space) of inner loop is identified, in which lies the computational expression that generates the output or outputs of the n-D problem. The processing elements (PE array) are assigned to the identified sub-space and the reuse of the PE array is through the assignment of the PE array to the successive sub-spaces in consecutive clock cycles/periods (CPs) to complete the computational tasks of the n-D problem. The above is used to develop our proposed modified heuristic search to arrive at optimal design and the complexity comparisons are given. The MATLAB results of the new search and the design space trade-off analysis using the high-level synthesis tool are presented for two typical computationally intensive nested loop algorithms-the 6D FSBM and the 4D edge detection alternatively known as the 2D filtering algorithm.

关键词： NESTED LOOPS Integration Level internal recycling Space Exploration algorithms MATLAB heuristic search Polyethylenes Surjective Systolic algorithms array structure

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Progress in high-linearity multi-element Josephson structures

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PHYSICA C-SUPERCONDUCTIVITY AND ITS APPLICATIONS 2010年第19期470卷 886-889页

作者： Kornev, Victor Soloviev, Igor Klenov, Nikolai Mukhanov, Oleg Moscow MV Lomonosov State Univ Dept Phys Moscow 119992 Russia Hypres Inc Elmsford NY 10523 USA

This paper summarizes both theoretical and experimental studies aimed at synthesis of high-linearity multi-element Josephson structures. Both the dynamic range and the voltage response linearity are two conjugated characteristics that must be improved jointly. Increase in dynamic range is reasonably associated with increase of number of elements N in the Josephson-junction structures. To improve the voltage response linearity one can use special design of the array structures. The other way is based on use novel basic cell with is bi-SQUID capable of providing highly linear voltage response. Both the approaches were used in designs of the reported high-linearity multi-element Josephson structures. (C) 2010 Elsevier B.V. All rights reserved.

关键词： Josephson junction dc SQUID array structure Dynamic range Linear voltage response Bi-SQUID

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Photolithography-free Ge-Se based memristive arrays;materials characterization and device testing

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CANADIAN JOURNAL OF PHYSICS 2014年第7-8期92卷 623-628页

作者： Latif, M. R. Csarnovics, I. Koekenyesi, S. Csik, A. Mitkova, M. Boise State Univ Dept Elect & Comp Engn Boise ID 83725 USA Boise State Univ Dept Elect & Comp Engn Boise ID 83725 USA Univ Debrecen Dept Expt Phys H-4012 Debrecen Hungary Hungarian Acad Sci Inst Nucl Res Debrecen Hungary

The focus of this work is on the formation of a lithography-free redox conductive bridge memristor array, comprised of different compositions of GexSe1-x chalcogenide glasses with the aim of selecting the chalcogenide material that provides the best performance. Various memristive arrays were fabricated on a metal-chalcogenide-metal stack. This structure offers high device density with the simplest configuration and allows access to each nano redox conductive bridge device. It was found that the device stability and threshold voltage were a function of the chalcogenide glass composition, with the Ge-rich film contributing to the best device performance, which is attributed to the formation of rigid structure and the availability of Ge-Ge bonds. Additionally, these parameters were dependent on the thickness and the surface roughness of the chalcogenide glass. Application of a nonlithography method for fabricating the array structure offered excellent yield, stable ON-OFF states and good uniformity. This demonstration, along with success achieved at the single cell level, suggests that the redox conductive bridge memristor is well positioned for ultrahigh performance memory and logic applications.

关键词： Photolithography-free arrays characterization RIGID structureS Memristors chalcogenide glasses cell level conductivity equipment performance device test Surface roughness array structure arrays threshold voltage

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Two-tuple balance of non-binary sequences with ideal two-level autocorrelation

Two-tuple balance of non-binary sequences with ideal two-lev...

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IEEE International Symposium on Information Theory

作者： Gong, Guang Song, Hong-Yeop Univ Waterloo Dept Elect & Comp Engn Waterloo ON N2L 3G1 Canada Yonsei Univ CITY Sch Elect & Elect Engn Seoul 120749 South Korea

Let p be a prime, q = p(m) and F-q be the finite field with q elements. In this paper, we will consider q-ary sequences of period q(n)-1 for q > 2 and study their various balance properties: symbol-balance, difference-balance, and two-tuple-balance properties. The array structure of the sequences is introduced, and various implications between these balance properties and the array structure are proved. Specifically, we prove that if a q-ary sequence of period q(n)-1 is difference-balanced and has the "cyclic" array structure then it is two-tuple-balanced. We conjecture that a difference-balanced q-ary sequence of period q(n)-1 must have the cyclic array structure. The conjecture is confirmed with respect to all of the known q-ary sequences which are difference-balanced, in particular, which have the ideal two-level autocorrelation function when q = p. (c) 2006 Elsevier B.V. All rights reserved.

关键词： non-binary PN sequences array structure balance property difference-balance property two-tuple-balance property ideal two-level autocorrelation cyclic difference sets with singer type parameters

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Development of a Highly Sensitive Humidity Sensor Based on a Piezoelectric Micromachined Ultrasonic Transducer array Functionalized with Graphene Oxide Thin Film

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SENSORS 2018年第12期18卷 4352-4352页

作者： Sun, Changhe Shi, Qiongfeng Yazici, Mahmut Sami Lee, Chengkuo Liu, Yufei Chongqing Univ Coll Optoelect Engn Ctr Intelligent Sensing Technol Chongqing 400044 Peoples R China Natl Univ Singapore Dept Elect & Comp Engn 4 Engn Dr 3 Singapore 117583 Singapore Natl Univ Singapore Ctr Intelligent Sensors E6 05-11F5 Engn Dr 1 Singapore 117608 Singapore Natl Univ Singapore MEMS E6 05-11F5 Engn Dr 1 Singapore 117608 Singapore Chongqing Univ Minist Educ Key Lab Optoelect Technol & Syst Chongqing 400044 Peoples R China Chongqing Univ Collaborat Innovat Ctr Brain Sci Chongqing 400044 Peoples R China

A novel relative humidity sensor that is based on a linear piezoelectric micromachined ultrasonic transducer (pMUT) array was proposed and microfabricated for high sensitivity, fast response, and good stability. The humidity-sensitive graphene oxide (GO) film was deposited on the pMUT array with a facile drop-casting method and characterized by scanning electron microscope (SEM), atomic force microscope (AFM), and Fourier transform infrared spectrum (FTIR). With the humidity level ranging from 10% to 90% RH, the sensor exhibited a high sensitivity of 719 Hz/% RH and an extremely high relative sensitivity of 271.1 ppm/% RH. The humidity-sensing results also showed good short-term repeatability and long-term stability, fast response and recovery, and low hysteresis. Moreover, the temperature coefficient of frequency (TCF) of the present humidity sensor was investigated and it could be easily compensated owing to the pMUT array structure design. This work confirmed that the GO functionalized pMUT is an excellent candidate in humidity detection and it may enable many potential applications, such as ultrasensitive mass detection and simultaneous detection of multiple parameters.

关键词： piezoelectric micromachined ultrasonic transducer humidity sensor graphene oxide array structure high sensitivity

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Linearity Analysis on a Series-Split Capacitor array for High-Speed SAR ADCs

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VLSI DESIGN 2010年第unknown期2010卷 706548-1-706548-8页

作者： Zhu, Yan Chio, U-Fat Wei, He-Gong Sin, Sai-Weng Seng-Pan, U. Martins, R. P. Univ Macau Analog & Mixed Signal VLSI Lab Fac Sci & Technol Macau Peoples R China Univ Tecn Lisboa Inst Super Tecn P-1049001 Lisbon Portugal

A novel Capacitor array structure for Successive Approximation Register (SAR) ADC is proposed. This circuit efficiently utilizes charge recycling to achieve high-speed of operation and it can be applied to high-speed and low-to-medium-resolution SAR ADC. The parasitic effects and the static linearity performance, namely, the INL and DNL, of the proposed structure are theoretically analyzed and behavioral simulations are peribrmed to demonstrate its effectiveness under those nonidealities. Simulation results show that to achieve the same conversion performance the proposed capacitor array structure can reduce the average power consumed from the reference ladder by 90% when compared to the binary-weighted splitting capacitor array structure.

关键词： Linearity Rescue array structure average power proposed structure Specific absorption rate

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A Scalable and Compact Systolic Architecture for Linear Solvers

A Scalable and Compact Systolic Architecture for Linear Solv...

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IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors (ASAP)

作者： Ong, Kevin S. H. Fahmy, Suhaib A. Ling, Keck-Voon Nanyang Technol Univ Sch Comp Engn Singapore 639798 Singapore Nanyang Technol Univ Sch Elect & Elect Engn Singapore 639798 Singapore

ISBN: (纸本)9781479936090

We present a scalable design for accelerating the problem of solving a dense linear system of equations using LU Decomposition. A novel systolic array architecture that can be used as a building block in scientific applications is described and prototyped on a Xilinx Virtex 6 FPGA. This solver has a throughput of around 3.2 million linear systems per second for matrices of size N= 4 and around 80 thousand linear systems per second for matrices of size N= 16. In comparison with similar work, our design offers up to a 12-fold improvement in speed whilst requiring up to 50% less hardware resources. As a result, a linear system of size N= 64 can be implemented on a single FPGA, whereas previous work was limited to a size of N= 12 and resorted to complex multi-FPGA architectures to scale. Finally, the scalable design can be adapted to different sized problems with minimum effort.

关键词： Linear system Scalability matrices Solvers ARCHITECTURE Linear system of equations Building construction Field programmable gate arrays Throughput array structure

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A disturb decoupled column select 8T SRAM cell 29

A disturb decoupled column select 8T SRAM cell

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IEEE Custom Integrated Circuits Conference

作者： Ramadurai, Vinod Joshi, Rajiv Kanj, Rouwaida IBM Syst & Technol Grp Essex Jct VT 05452 USA IBM T J Watson Res Lab Yorktown Hts NY USA IBM Austin Res Labs Austin TX USA

ISBN: (纸本)9781424407866

This paper presents a novel 8 transistor SRAM cell that can be used for enhancing cell Vdd(min) at and beyond 90nm technology nodes. This cell provides a way to eliminate the column select read disturb scenario in SRAMS which is one of the impediments to lowering cell voltage. Read disturbs to the selected cell are then minimized by relying on a sense-amp based array architecture which enables discharging the bit-line (BL) capacitance to GND during a read operation thereby enhancing its low voltage operability. The sensitivity of the cell to BL height and sense timing has been studied and the feasibility of the cell has been proved by fabricating a 32Kb array in a 90mn PD/SOI technology. Hardware experiments and simulation results show improvements of cell Vdd(min) over traditional 6T cells by more than 150mV for 90mn PD/SOI technology.

关键词： array structure cell voltage DECOUPLING read operation Simulation results

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Progress in high-linearity multi-element Josephson structures

Progress in high-linearity multi-element Josephson structure...

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6th International Conference on Vortex Matter in Nanostructured Superconductors

作者： Kornev, Victor Soloviev, Igor Klenov, Nikolai Mukhanov, Oleg Moscow MV Lomonosov State Univ Dept Phys Moscow 119992 Russia Hypres Inc Elmsford NY 10523 USA

关键词： Josephson junction dc SQUID array structure Dynamic range Linear voltage response Bi-SQUID

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Simplified Design of 6: 1 PUMA arrays

Simplified Design of 6: 1 PUMA Arrays

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IEEE International Symposium on Antennas and Propagation / USNC/URSI National North American Radio Science Meeting

作者： Lee, Michael Y. Logan, John T. Kindt, Rick W. Vouvakis, Marinos N. Univ Massachusetts Dept Elect & Comp Engn Amherst MA 01003 USA Naval Res Lab Div Radar Washington DC 20375 USA

ISBN: (纸本)9781479978151

Advances in Planar Ultra-wideband Modular Antenna (PUMA) array architecture which have culminated into a 6: 1 bandwidth design without the use of an external backplane matching network are presented. This paper will examine the additional bandwidth-enhancing operational principles of the proposed dual-polarized 6: 1 PUMA array. A design and its respective full-wave simulations will then be presented, with results yielding a 6: 1 bandwidth with VSWR < 2 at broadside, VSWR < 2.6 scanning out to theta = 45 degrees, and a diagonal plane cross-polarization greater than 15 dB at theta = 45 degrees for the majority of the band.

关键词： Standing wave ratios array structure Bandwidth bottom plates matching network arrays

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