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IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)

作者： Nukala, Nishant. S. Kulkarni, Niranjan Vrudhula, Sarma Arizona State Univ Sch Comp Informat & Decis Syst Engn Tempe AZ 85281 USA

ISBN: (纸本)9781450316712

This paper describes a novel, first of its kind architecture for a threshold logic gate using conventional MOSFETs and an STT-MTJ (Spin Torque Transfer-Magnetic Tunnelling Junction) device. The resulting cell, called STL which is extremely compact can be programmed to realize a large number of threshold functions, many of which would require a multilevel network of conventional CMOS logic gates. Next, we describe a novel array architecture consisting of STL cells onto which complex logic networks can be mapped. The resulting array, called STLA has several advantages not available with conventional logic. This type of logic (1) is non-volatile, (2) is structurally regular and operates like DRAM, (3) is fully observable and controllable, (4) has zero standby power. These advantages are demonstrated by implementing a 16-bit carry look-ahead adder and compared with two optimized conventional FPGA implementations (Carry Look Ahead Adder and Ripple Carry Adder). The STLA has 12X lower transistor count (compared to CLA-FPGA) and 10X reduction (compared to RCA-FPGA) with comparable energy which will continue to reduce as the STT-MTJ device technology matures.

关键词： Junction matures implementations Junction Device Component Crossing threshold logic Maturity semi-threshold logic array structure Logic arrays Compact Compact Pattern carry look-ahead adder Building construction ARCHITECTURE

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An FPGA-Based Systolic array to Accelerate the BWA-MEM Genomic Mapping Algorithm 15

An FPGA-Based Systolic Array to Accelerate the BWA-MEM Genom...

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International Conference on Embedded Computer Systems Architectures Modeling and Simulation

作者： Houtgast, Ernst Joachim Sima, Vlad-Mihai Bertels, Koen Al-Ars, Zaid Delft Univ Technol Fac EEMCS Delft Netherlands

ISBN: (纸本)9781467373111

We present the first accelerated implementation of BWA-MEM, a popular genome sequence alignment algorithm widely used in next generation sequencing genomics pipelines. The Smith-Waterman-like sequence alignment kernel requires a significant portion of overall execution time. We propose and evaluate a number of FPGA-based systolic array architectures, presenting optimizations generally applicable to variable length Smith-Waterman execution. Our kernel implementation is up to 3x faster, compared to software-only execution. This translates into an overall application speedup of up to 45%, which is 96% of the theoretically maximum achievable speedup when accelerating only this kernel.

关键词： Systolic algorithms execution time acceleration Genomics Sequence Alignment Seeds Speeding array structure Legal Executions Kernel

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Airborne GMTI Clutter Suppression Performance Utilizing AWideband Sparse array

Airborne GMTI Clutter Suppression Performance Utilizing AWid...

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5th IEEE International Symposium on Phased array Systems and Technology

作者： Jao, Jen King MIT Lincoln Lab Lexington MA 02420 USA

ISBN: (纸本)9781467311274

Airborne multichannel SAR-GMTI radar is capable of detecting very slow moving targets on the ground. Such radar may employ a large sparse antenna array, a wideband waveform, and long CPI to simultaneously achieve strong clutter cancellation and fine spatial resolution in the cross-track range and the along-track cross range dimensions. In this paper, analytic solutions of the target signal-to-noise ratio (SNR) loss will be presented to characterize the clutter cancellation performance of adaptive array processing. The closed-form expression of the SNR loss may be conveniently used to trade off SAR-GMTI radar design parameters such as the SAR integration angle, the waveform spectrum, and the sparse array structure without the need of executing numerical simulations with excessive computational load.

关键词： clutter cancellation clutter suppression array structure adaptive antenna arrays Closed-form solutions signal to noise ratios radar broadband airborne tracking range Supernova remnants waveforms Spatial resolution

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High-Frequency Symmetric Multiphase array Coupled Inductors for Interleaved Bidirectional DC-DC Converters 13

High-Frequency Symmetric Multiphase Array Coupled Inductors ...

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13th IEEE Conference on Industrial Electronics and Applications (ICIEA)

作者： Wang, Lei Zhang, Donglai Duan, Jinpei Li, Jiannong Harbin Inst Technol Shenzhen Grad Sch Power Elect & Mot Control Res Ctr Shenzhen 518055 Peoples R China

ISBN: (纸本)9781538637586

In order to improve high frequency characteristics of converters, eliminate DC bias and realize symmetric coupling, this paper presents a new kind of high-frequency, symmetric and matrix integrated inductors on the basis of unit coupled magnetic cores and their flexible combinations. It equivalently segments magnetic cores and windings of traditional coupled inductors by reversely deducing topological multiplexing, combines magnetic fields with electric fields and circuits and integrates multi-scale analysis methods of circuit equivalent transformation to explore mechanisms of integrated magnetics in eliminating DC bias, freely adjusting coupling degree and arbitrarily expanding integration phases, thereby deriving principles of designing high-frequency symmetric integrated magnetics. Finally, two-phase and four-phase experiments are carried out to demonstrate correctness of the matrix structure and its output advantages in high-frequency IBDC.

关键词： array structure high-frequency bidirectional DC-DC unit coupled magnetic core symmetry DC bias

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array designs for active electrically small superconductive antennas

Array designs for active electrically small superconductive ...

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VORTEX 7th Conference

作者： Kornev, Victor Soloviev, Igor Klenov, Nikolai Sharafiev, Alexey Mukhanov, Oleg Moscow MV Lomonosov State Univ Dept Phys Moscow 119991 Russia Moscow MV Lomonosov State Univ Skobeltsyn Inst Nucl Phys Moscow 119991 Russia Hypres Inc Elmsford NY 10523 USA

Active electrically small superconductive antennas based on serial arrays of the cells capable of providing highly linear voltage response to magnetic signal were proposed and developed. Two different basic cells were devised. The first one is bi-SQUID, and the second one is the cell consisting of two parallel SQIFs connected in differential way. The antenna prototypes were designed, fabricated and evaluated. The mostly efficient antenna prototype occupied area of 3.3 mm x 3.3 mm was characterized by the transfer factor dV/dB of about 750 mV/mT and the transfer function linearity up to 70 dB. (C) 2012 Elsevier B.V. All rights reserved.

关键词： Josephson junction Dc SQUID array structure Dynamic range Linear voltage response Bi-SQUID

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Research of Bulk Erase Operation in Vertical Three-Dimensional Cell array Architecture

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JAPANESE JOURNAL OF APPLIED PHYSICS 2013年第4期52卷 04CD14-04CD14页

作者： Yang, Hyung-jun Lee, Gae-hun Kim, Kyeong-rok Song, Yun-heub Hanyang Univ Dept Elect Engn Seoul 133791 South Korea

A bit-cost scalable (BiCS) NAND flash memory with a bulk erasing method is investigated in view of cell characteristics and uniformity. The proposed cell array has an additional electrode layer for a bulk erase operation in the middle of a vertical channel string cell. Here, under a bias condition of 20 V, a programming threshold voltage of 4.2 V at 1 ms and an erasing threshold voltage of Vth = -1.5 V at 10 ms are confirmed, which is acceptable for flash memories. Furthermore, the shielding transistor close to an erase electrode is also investigated, which gives better erase characteristics for the cells adjacent to the erase electrode. From this result, we expect that a bulk erasable-BiCS technology with a shielding transistor can be a candidate three-dimensional (3D) NAND flash memory. (C) 2013 The Japan Society of Applied Physics

关键词： flash memories Volume Electrodes cell array Transistor Device Component Shield vertical array structure Surgery threshold voltage Vanadium

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MCMA: A modular processing elements array based low-power coarse-grained reconfigurable accelerator

MCMA: A modular processing elements array based low-power co...

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International Conference on Reconfigurable Computing and FPGAs (ReConFig)

作者： Chaintreuil, Remi Uno, Rie Amano, Hideharu Keio Univ Dept Informat & Comp Sci Yokohama Kanagawa 223 Japan

ISBN: (纸本)9781479920785

The Cool Mega-array is a highly power-efficient coarse-grained reconfigurable accelerator, particularly aimed toward multimedia applications executed on battery-driven devices. It consists of a large processing elements array, without any memory element, a simple micro-controller for data management and the data memory. The power consumption of the PE array itself is very low, and can be further reduced by dynamically scaling its power voltage in order to adapt to the desired speed of computation. A modular version of this design is proposed, which provides the ability to reconfigure the PE array structure, and adapt its size to the application. This allows the execution of applications with different complexities and degrees of parallelism on a relatively smaller chip, compared to simply using a large PE array, depending on the implementation choices and the set of applications (4 times less processing elements in the implementation example). Power-leakage can also be reduced by using coarse-grained power-gating.

关键词： array structure desired speed Data storage devices Polyethylenes memory element configurability Modularity Data management MULTIMEDIA APPLICATION Elements parallelism Power consumption LOW POWER arrays Legal Executions

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Design of three Wide-Bandwidth Terahertz array Antennas Based on Composite Right/Left-Handed Transmission Line

Design of three Wide-Bandwidth Terahertz Array Antennas Base...

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IEEE International Conference on Ultra-WideBand (ICUWB)

作者： Zhu, Ningli Chen, Jing Zhang, Wei Xu, Kaisi Peking Univ Inst Microelect Beijing Peoples R China

ISBN: (纸本)9781479953967

Three metamaterial-inspired terahertz antennas using negative order resonance are proposed and analyzed in this paper. The design of these novel resonant-type antennas which can be realized by traditional MEMS technology are based on the study of a composite right/left-handed transmission line (CRLHTL). These antennas have content terahertz radiation characteristics. The slots act as a series capacitors as well as radiators can perform a CRLH antenna application. Three antennas with three or more CRLH unit cells are simulated. Compared with the existing antennas, our antennas show advantages in simplicity and wideband.

关键词： MEMS composite right/left-handed CRLH array structure THz

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Systolic-array Architecture for 2D IIR Wideband Dual-Beam Space-Time Plane-wave Filters

Systolic-Array Architecture for 2D IIR Wideband Dual-Beam Sp...

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53rd Midwest Symposium on Circuits and Systems (MWSCAS 2010)

作者： Wijenayake, Chamith Madanayake, Arjuna Bruton, Len T. Univ Akron Akron OH 44325 USA Univ Calgary Elect & Comp Engn Calgary AB T2N 1N4 Canada

ISBN: (纸本)9781424477739

A spatio-temporal 2D IIR broadband plane-wave filter having 2 user-selectable passbands is proposed using the concept of 2D network resonance. The plane-wave filter is capable of the highly-selective directional enhancement of 2 far-field plane-waves in the presence of undesired waves at different directions of arrival. A massively-parallel systolic-array processor architecture is proposed for the real-time VLSI implementation of the filter. The architecture is designed, simulated, and implemented as a prototype clocked at 50 MHz, using a Xilinx Virtex-4 Sx35-10ff668 FPGA device. The proposed systolic-array delivers a real-time throughput of one-frame-per-clock-cycle (OPFCC) which implies 50 million linear frames per second. The design is simulated (for a 32 element array) and tested on-chip (for an 18-element array) using 2D impulse-and frequency-responses, and using multi-directional broadband plane-wave test sequences.

关键词： Plane waves Filters synchrone Butyl rubber array structure Frequency filters broadband array Element Building construction ARCHITECTURE dual beam

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Development of a compacted doubly nesting array in Narrow Scribe Line aimed at detecting soft failures of interconnect via

Development of a compacted doubly nesting array in Narrow Sc...

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IEEE International Conference on Microelectronic Test structures (ICMTS)

作者： Shinkawata, Hiroki Tsuboi, Nobuo Tsuda, Atsushi Sato, Shingo Yamaguchi, Yasuo Renesas Elect Corp Prod & Technol Unit 751 Horiguchi Hitachinaka Ibaraki 3128504 Japan Renesas Syst Design Corp Kodaira Tokyo 1878588 Japan Kansai Univ Suita Osaka 5648680 Japan

ISBN: (纸本)9781479983049

We introduce a new addressable test structure array using for mass production stage which is compacted doubly nesting array into Narrow Scribe Line which named as High sensitivity-Screening and Detection-decoder test structure in Scribe line (HSD-S). Abnormally high resistance as a soft failure via was detected and located in a 40nm CMOS technology. We captured a soft failure bit which had a high resistance via exhibiting over 160 times larger one.

关键词： Scribe line array structure soft failure Back End Of Line interconnect via variability yield

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