The impact of Electromigration (EM) on the Bit-Error-Rate (BER) of signal interconnect paths was experimentally examined. An array-based test-vehicle for tracking Bit-Error-Rate (BER) degradation of signal interconnec...
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The impact of Electromigration (EM) on the Bit-Error-Rate (BER) of signal interconnect paths was experimentally examined. An array-based test-vehicle for tracking Bit-Error-Rate (BER) degradation of signal interconnects subject to Direct-Current (DC) EM stress was implemented in a 16nm FinFET process. A unit interconnect path comprises five identical interconnect stages where each wire is driven by inverter based buffers. Accelerated EM stress testing is achieved entirely on-chip using metal heaters located directly above the devices-under-test (DUTs) and separate stress circuits driving both ends of the wire. The proposed test structure features a ring-based Voltage-Controlled-Oscillator (VCO), a bit-pattern generator and local BER sampling monitors which enable bitwise tracking of '0' and '1' errors separately, further simplifying the overall test-setup and allowing for high precision characterization of EM induced resistance shifts using only digital circuits. Measurement data collected from the 16nm prototype reveals unique insights into EM induced signal path degradation that was not available prior to this work. Our experimental studies suggest that monitoring the BER of an interconnect path could be used as a new metric for capturing EM induced resistance shifts in a real system, in lieu of the conventional approach which focuses on monitoring standalone wire resistances. Supplemental simulations showcasing the projected degradation in the interconnect path operating frequency as a function of stress time constructed from resistance traces sampled from identical wires implemented in the same process reaffirm the measurement trends.
Current VLSI design techniques focus on four major goals: higher integration, faster speed, lower power, and shorter time-to-market. These goals have been accomplished mainly by deep submicron (DSM) technology along w...
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Current VLSI design techniques focus on four major goals: higher integration, faster speed, lower power, and shorter time-to-market. These goals have been accomplished mainly by deep submicron (DSM) technology along with voltage scaling. However, scaling down of feature size causes larger interwire capacitance which results in large crosstalk between interconnects. In this paper, we propose a novel predictable circuit architecture, named "optimized overlaying array-based architecture" (O(2)ABA), especially suited for the deep submicron regime. O(2)ABA achieves reduction in crosstalk by considering the current directions and by reducing interwire capacitance. The introduction of "unit cell" leads to regularity, which makes the performance predictable even before layout, and shortens design time. O(2)ABA is compared with other design styles, such as custom design and standard cell approach, in terms of coupling capacitance, area, and delay.
Microdeletions within chromosome 22q11.2 cause a variable phenotype, including DiGeorge syndrome (DGS) and velocardiofacial syndrome (VCFS). About 97% of patients with DGS/VCFS have either a common recurrent similar t...
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Microdeletions within chromosome 22q11.2 cause a variable phenotype, including DiGeorge syndrome (DGS) and velocardiofacial syndrome (VCFS). About 97% of patients with DGS/VCFS have either a common recurrent similar to 3 Mb deletion or a smaller, less common, similar to 1.5 Mb nested deletion. Both deletions apparently occur as a result of homologous recombination between nonallelic flanking low-copy repeat (LCR) sequences located in 22q11.2. Interestingly, although eight different LCRs are located in proximal 22q, only a few cases of atypical deletions utilizing alternative LCRs have been described. Using array-based comparative genomic hybridization (CGH) analysis, we have detected six unrelated cases of deletions that are within 22q11.2 and are located distal to the similar to 3 Mb common deletion region. Further analyses revealed that the rearrangements had clustered breakpoints and either a similar to 1.4 Mb or similar to 2.1 Mb recurrent deletion flanked proximally by LCR22-4 and distally by either LCR22-5 or LCR22-6, respectively. Parental fluorescence in situ hybridization (FISH) analyses revealed that none of the available parents (11 out of 12 were available) had the deletion, indicating de novo, events. All patients presented with characteristic facial dysmorphic features. A history of prematurity, prenatal and postnatal growth delay, developmental delay, and mild skeletal abnormalities was prevalent among the patients. Two patients were found to have a cardiovascular malformation, one had truncus arteriosus, and another had a bicuspid aortic valve. A single patient had a cleft palate. We conclude that distal deletions of chromosome 22q11.2 between LCR22-4 and LCR22-6, although they share some characteristic features with DGS/VCFS, represent a novel genomic disorder distinct genomically and clinically from the well-known DGS/VCF deletion syndromes.
Nowadays, there are a number of algorithms that have been proposed in frequent itemsets mining (FIM). Data projection is one of the key features in FIM that affects the overall performance. The aim is to speed up the ...
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ISBN:
(纸本)9789812879363;9789812879356
Nowadays, there are a number of algorithms that have been proposed in frequent itemsets mining (FIM). Data projection is one of the key features in FIM that affects the overall performance. The aim is to speed up the searching process by rearranging the items in a more compact form and to fit all the items in the data set in main memory efficiently without losing any information. The data refer to how the data set is stored in the main memory before the mining process begin. This paper explores the effects of data projection on frequent itemset mining from three different data projection types which are FP-Tree (tree-based), H-Struct (array-based) and FP-Graph (graph-based). The time construction and memory consumption are used to evaluate the parse and the dense of the data set. The result showed the construction of H-Struct is the fastest, but it consumes more time to mine frequent itemsets compared with FP-Tree and FP-Graph.
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