Process variation results in up to an order of magnitude variation in on/off ratios, which significantly depresses the yield of the sub-thresholdcircuits. This paper presents low power sub-thresholdadders using sens...
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(纸本)9781467397209
Process variation results in up to an order of magnitude variation in on/off ratios, which significantly depresses the yield of the sub-thresholdcircuits. This paper presents low power sub-thresholdadders using sense amplifier-based pass transistor logic(SAPTL). based on the simulations in 130 nm CMOS process, the proposed two-phase synchronous SAPTL adder exhibits stronger robustness to process variations when compared to the ripple carry adder using standard cell circuits. And the adderbased on ADSA-SAPTL features much less power consumption than synchronous SAPTL adder.
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