In this work, modified histogramestimation (MHE) architecture is proposed to verify the histogram count in the FPGA platform, and the basic HE (BHE) architecture is also implemented for comparative purpose. The entir...
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In this work, modified histogramestimation (MHE) architecture is proposed to verify the histogram count in the FPGA platform, and the basic HE (BHE) architecture is also implemented for comparative purpose. The entire proposed MHE architecture is developed newly so as to reduce the logical elements involved in the HE process. In MHE architecture, dual port read only memory (DPROM), carry select adder based counter (CSAC), and Optimal Bin Counter (OBC) are used to evaluate the HE count with effective accuracy. The amount of percentage reduced by the 256 sample MHE is 17.62%, 15.41% and 23.01% for area, power and delay respectively. Additionally, the performance of the proposed MHE is compared with four existing methods HOG, HBS, MBPA and DMH. The number of flip flops utilised by the MHE architecture is 2177 for Vertex 6 device, which is less compared to the HOG and MBPA.
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