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10th Spintronics Symposium

作者： Friedman, Joseph S. Univ Texas Dallas Dept Elect & Comp Engn Richardson TX 75080 USA

ISBN: (数字)9781510611726

ISBN: (纸本)9781510611726;9781510611719

Though numerous spintronic switching devices have been proposed or demonstrated, there has been significant difficulty in translating these advances into practical computing systems. The challenge of cascading has impeded the integration of multiple devices into a logic family, and several proposed solutions potentially overcome these challenges. Here, the cascading techniques by which the output of each spintronic device can drive the input of another device are described for several logic families, including spin-diode logic (in particular, all-carbon spin logic), complementary magnetic tunnel junction logic (CMAT), and emitter-coupled spin-transistor logic (ECSTL).

关键词： spin-diode logic graphene nanoribbon carbon nanotube all-carbon spin logic complementary magnetic tunnel junction logic emitter-coupled spin-transistor logic spintronic logic beyond-cmos computing

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High-performance spintronic computing with magnetoresistive semiconductor heterojunctions

High-performance spintronic computing with magnetoresistive ...

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SPIE Symposium on Spintronics VI

作者： Friedman, Joseph S. Wessels, Bruce W. Sahakian', Alan V. Northwestern Univ Evanston IL 60208 USA

ISBN: (纸本)9780819496638

Two recently proposed spintronic logic families, spin-diode logic and emitter-coupled spin-transistor logic, provide an opportunity for high-performance cascaded logic circuits. These logic families make use of magnetoresistive semiconductor heterojunctions, in which the presence of a magnetic field causes a large increase in resistance. Spin-diode logic and emitter-coupled spin-transistor logic produce highly compact circuits with superior speed and power characteristics. In particular, circuits realized in these logic families use three to ten times fewer devices than conventional cmos. Additionally, there is minimal dynamic power dissipation, presenting a pathway for low power high performance computing beyond 10 GHz.

关键词： Spintronics beyond-cmos computing spin-diode logic emitter-coupled spin-transistor logic magnetoresistive semiconductor heterojunction spintronic logic emerging technology next generation computing

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Quantum-Dot Cellular Automata: A Clocked Architecture for High-Speed, Energy-Efficient Molecular computing 16th

Quantum-Dot Cellular Automata: A Clocked Architecture for Hi...

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16th International Conference on Unconventional Computation and Natural Computation (UCNC)

作者： Blair, Enrique P. Baylor Univ Waco TX 76798 USA

ISBN: (纸本)9783319581873;9783319581866

Quantum-dot cellular automata (QCA) is a non-transistorbased, classical computing paradigm. QCA devices may be implemented using mixed-valence molecules, and logic circuits are formed by laying out ordered arrays of QCA molecules on a substrate. Molecules are locally coupled via the Coulomb field. The molecular circuits can be clocked using an applied perpendicular electric field. A fully-quantum model of fielddriven electron transfer (ET) is used to determine the ET rate for specific QCA candidate molecules. The diferrocenyl acetylene (DFA) molecule is taken as an example QCA molecule, and this model indicates DFA may support classical computation at speeds well beyond the GHz range.

关键词： Molecular classical computing High-speed computing beyond-cmos computing Energy-efficient computing

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CMAT Non-Volatile Spintronic computing: Complementary MTJ Logic 9

CMAT Non-Volatile Spintronic Computing: Complementary MTJ Lo...

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9th Spintronics Symposium / SPIE Conference

作者： Friedman, Joseph S. Univ Texas Dallas Dept Elect Engn Richardson TX 75080 USA

ISBN: (纸本)9781510602540

Magnetic tunnel junctions (MTJs) have thoroughly demonstrated their utility as a non-volatile memory storage element, inspiring their application to a memory-in-logic computer that would overcome the von Neumann bottleneck. However, MTJ logic gates must be able to cause other MTJs to switch, thus ensuring the cascading capability fundamental to efficient computing. Complementary MTJ logic (CMAT) provides a simple circuit structure through which MTJs can be cascaded directly to perform logic operations. In this novel logic family, charge pulses resulting from MTJ switching create magnetic fields that switch other MTJs, providing impetus for further development of MTJs for computing applications.

关键词： magnetic tunnel junction spintronic logic beyond-cmos computing magnetoresistance complementary magnetic tunnel junction logic CMAT non-von Neumann architecture

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An examination of Post-cmos computing techniques using steep-slope device-based architectures

An examination of Post-CMOS computing techniques using steep...

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作者： Swaminathan, Karthik Venkataraman PennState University Libraries

学位级别：Doctor of Philosophy

As technology scaling results in smaller and smaller transistor sizes, existing cmostechnology starts to encounter certain fundamental physical limitations. These limitations canpotentially result in drastic reduction in performance and energy efficiencies of these transistors,which could make it untenable to continue scaling them. This in turn, would severely limit thebenefits of further innovations in processor design and architecture. In this scenario, there havebeen several alternatives proposed at the device level. However, each of these devices comeswith varying energy-performance tradeoffs and optimal design points in comparison to cmostechnology. Hence, there is a need for a rethink of the complete design hierarchy, ranging from asimple circuit to entire processor platforms. In my work, I attempt to answer the question, Doesa better device make a better processor?, by examining the impact of varying device parametersat the architecture-level. I carry out a comprehensive exploration of different design points, at themicro-architecture and architecture levels of abstraction and examine the feasibility of deviceheterogeneousarchitectures for achieving greater regions of optimality. My work also extendsto gauging the impact of using these emerging technologies on non-traditional architectures,including domain specific accelerators and 3D-stacked processors.

关键词： beyond-cmos computing Heterojunction Tunnel FET (TFET) device-to-architecture abstraction heterogeneous architectures

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Karnaugh Map Method for Memristive and Spintronic Asymmetric Basis Logic Functions

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IEEE TRANSACTIONS ON COMPUTERS 2021年第1期70卷 128-138页

作者： Vyas, Vaibhav Jiang-Wei, Lucian Zhou, Peng Hu, Xuan Friedman, Joseph S. Univ Texas Dallas Dept Elect & Comp Engn Richardson TX 75080 USA

The development of beyond-cmos technologies with alternative basis logic functions necessitates the introduction of novel design automation techniques. In particular, recently proposed computing systems based on memristors and bilayer avalanche spin-diodes both provide asymmetric functions as basis logic gates - the implication and inverted-input AND, respectively. This article therefore proposes a method by which Karnaugh maps can be directly applied to systems with asymmetric basis logic functions. A set of identities is defined for these memristor and spintronic logic functions, enabling the formal demonstration of the Karnaugh map method and an explanation of the proposed technique. This method thus, enables the direct minimization of spintronic and memristive logic circuits without translation to conventional Boolean algebra, facilitating the further development of these novel computing paradigms. Preliminary analyses demonstrate that this Karnaugh map minimization approach can provide a 28 percent reduction in step count as compared to previous manual optimization.

关键词： Memristors Logic gates Logic functions Minimization Performance evaluation Spintronics Resistance Boolean algebra beyond-cmos computing asymmetric logic emerging technologies memristors spintronics

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Threshold Logic With Electrostatically Formed Nanowires

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IEEE TRANSACTIONS ON ELECTRON DEVICES 2016年第3期63卷 1388-1391页

作者： Friedman, Joseph S. Godkin, Andrey Henning, Alex Vaknin, Yonatan Rosenwaks, Yossi Sahakian, Alan V. Univ Paris Saclay CNRS Univ Paris 11 Inst Elect Fondamentale F-91405 Orsay France Tel Aviv Univ Sch Elect Engn IL-6997801 Tel Aviv Israel Northwestern Univ Dept Elect Engn & Comp Sci Evanston IL 60208 USA

The modulation of current through an electrostatically formed nanowire (EFN) is controlled by the voltage on the four input gates. The behavior of this multi-gate transistor can be interpreted as a complex four-input switching process, enabling the computation of multiple-input threshold logic functions using a single device. We have therefore created a novel threshold logic family leveraging these unique capabilities that enables the efficient computation of complex logic functions. Experimental and simulation data are provided to demonstrate feasibility and evaluate behavior. This logic family overcomes the challenge posed by the input-output voltage mismatch inherent to EFNs and produces circuits with one-eighth the number of active logic devices and one-quarter the number of transistors required by cmos.

关键词： beyond-cmos computing FETs nanowire threshold logic

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Voltage-controlled topological-spin switch for ultra-low-energy computation 11

Voltage-controlled topological-spin switch for ultra-low-ene...

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11th Spintronics Symposium

作者： Rakheja, Shaloo Flatte, Michael E. Kent, Andrew D. NYU Dept Elect & Comp Engn Brooklyn NY 11201 USA Univ Iowa Dept Phys & Astron Iowa City IA 52242 USA Univ Iowa Opt Sci & Technol Ctr Iowa City IA USA Ctr Quantum Phenomena Dept Phys New York NY USA

ISBN: (数字)9781510620360

ISBN: (纸本)9781510620360

In this paper, we present the functionality and model the performance of a new spin-based logic device called the voltage-controlled topological-spin switch (vTOPSS). This device stores information in the magnetization of a thin magnetic insulator (MI) layer, which has ultra-fast dynamics and low-energy dissipation due to its small damping factor. To control the magnetization of the MI, a voltage signal is applied to a proximal topological insulator (TI) layer, which has a high charge-to-spin conversion efficiency at room temperature. The information in the MI layer is read using a magnetic tunnel junction (MTJ) voltage divider with sub-100 mV read voltages. Since its input/output state variables are in the voltage domain, the vTOPSS device does not require any transduction circuitry to be integrated with the cmos technology. Device optimization shows that the vTOPSS device can operate with sub-25 aJ energy dissipation and < 30 nW power in on-state-these values are much lower than those reported in contemporary spin-based devices. Results confirm that the dominant component of energy dissipation is due to the TI leakage, which can be reduced by suppressing the surface and bulk charge conduction in the TI. Unlike cmos devices, energy dissipation of the VTOPSS device is proportional to its switching delay. To simultaneously achieve low latency and energy dissipation in vTOPSS, a TI material with a large spin Hall conductivity and negligible charge conductivity is preferred. Interconnect burden on the performance of the vTOPSS device is minimal, which opens up the possibility of using highly resistive nanowires as potential interconnects for this technology.

关键词： beyond-cmos computing topological spintronics magnetic insulator performance modeling

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Cascaded Spintronic Logic Gates based on Graphene Nanoribbon Magnetoresistance: All-Carbon Spin Logic 11

Cascaded Spintronic Logic Gates based on Graphene Nanoribbon...

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11th Spintronics Symposium

作者： Friedman, Joseph S. Univ Texas Dallas Dept Elect & Comp Engn Richardson TX 75080 USA

ISBN: (数字)9781510620360

ISBN: (纸本)9781510620360

The extremely large magnetoresistance demonstrated with graphene nanoribbons (GNRs) is highly attractive as a potential spintronic switch. To develop a computing system in which GNRs can be cascaded requires a mechanism for transforming the GNR resistance into a magnetic field that can activate the magnetoresistance of other GNRs. All-carbon spin logic provides this necessary direct cascading by routing the GNR current through carbon nanotubes (CNTs) positioned adjacent to other GNRs. Applying a constant voltage bias across each CNT-GNR-CNT path results in a magnetic field-dependent electrical current that can perform logical functions, providing a scaling path toward large-scale computing systems.

关键词： graphene nanoribbon carbon nanotube all-carbon spin logic spintronic logic beyond-cmos computing spin-diode logic

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Magnetoresistance Implications for Complementary Magnetic Tunnel Junction Logic (CMAT)

Magnetoresistance Implications for Complementary Magnetic Tu...

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IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)

作者： Friedman, Joseph S. Querlioz, Damien Sahakian, Alan V. Univ Paris 11 CNRS Inst Elect Fondamentale Orsay France Northwestern Univ Dept Elect Engn & Comp Sci Evanston IL USA

ISBN: (纸本)9781467378499

This concept paper provides a first quantitative analysis of complementary magnetic tunnel junction logic (CMAT), a novel cascaded logic family composed solely of magnetic tunnel junctions (MTJs). CMAT is a non-volatile logic family driven by field-induced spin-switching that was inspired by cmos. A compact CMAT multiplexer is presented, and the impact of magnetoresistance on its behavior is analyzed. The efficiency of CMAT is shown to be a function of the MTJ magnetoresistance, providing impetus for further development of MTJs for computing applications.

关键词： spintronic logic magnetic tunnel junction beyond-cmos computing non-Von Neumann architecture

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