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2025 Conference on Practical Holography-Displays, Materials, and Applications

作者： Muhamad, Raees Kizhakkumkara Blinder, David Schelkens, Peter Vrije Univ Brussel VUB Dept Elect & Informat ETRO Pleinlaan 2 B-1050 Brussels Belgium IMEC Kapeldreef 75 B-3001 Leuven Belgium

ISBN: (纸本)9781510685284;9781510685291

We showcase INTERFERE, a hologram compression framework selected as the basis of the JPEG Pleno Holography standard. It supports view-dependent coding with simultaneous spatial and angular random access. INTERFERE utilizes an adaptive quantization mechanism that can assign a variable bit width across small phase-space regions. This ensures that the transform coefficients are compactly represented before entropy coding. In this work, we design a new entropy coding mechanism with division-free binary arithmetic coding, allowing us to better capitalize on the compact quantized representation. We also create new probability models for driving the binary arithmetic coder, which can fully harness SIMD instructions while exhibiting significantly smaller memory requirements, enabling it to reside in the CPU cache. Speed-ups ranging from 6x - 600x in decoding and encoding times on the CPU were achieved over our previous solution without compromising rate-distortion performance. With this work, we propose a practical hologram codec that is class-leading in rate-distortion performance, ease of random access, and encoding/decoding throughput, thereby providing a practical solution to one of digital holography's most pressing challenges.

关键词： hologram compression STFT entropy coding binary arithmetic coding high throughput SIMD

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An efficient image compression architecture based on optimized 9/7 wavelet transform with hybrid post processing and entropy encoder module

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MICROPROCESSORS AND MICROSYSTEMS 2023年 98卷

作者： Pranitha, K. Kavya, G. Anna Univ SA Engn Coll Dept Informat & Commun Engn Chennai 600077 India Anna Univ SA Engn Coll Dept Elect & Commun Engn Chennai 600077 India

Satellite communication is popular due to the advancement in storing and transmitting satellite images. Image compression can be defined as the science of lowering the number of bits necessary to represent an image. In satellite image processing, image degradation is considered a challenging problem. The Consultative Committee for Space Data Systems (CCSDS) Image Data Compression (IDC) standard CCSDS-122.0-B-1 is the transformation-dependent image compression method developed especially for usage in on-board space platforms. It holds de-correlation, quantization and entropy encoding phases. This paper introduces a new optimized memory organization for Discrete Wavelet Transform (DWT) to perform spatial de-correlation with fewer memory requirements on an FPGA device. Also, the proposed optimized DWT is integrated with a hybrid post-processing and entropy encoder module to reduce the spatial redundancies between the wavelet coefficients and compress the de-correlated data with high compression performance. A high-throughput hardware implementation of the binary arithmetic entropy Coder (BAEC) is also provided to perform lossless compression with low implementation complexity. To provide the convenience and compactness, the proposed system will be implemented in the Xilinx working platform by developing a Verilog code. The proposed model is then evaluated on the Arty Z7-20 development board. The proposed approach is analyzed on different performance parameters such as throughput and frequency. The proposed design allowed a maximum operating frequency of 250 MHz, leading to a throughput of 156.25 Msamples/sec on Zynq. In addition, the structure of the proposed method overtakes the conventional design in terms of memory requirements and area.

关键词： CCSDS-122.0-B-1 Discrete wavelet transform (DWT) Entropy encoder binary arithmetic coding Memory organization Compression and post -processing

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Generative Multi-Symbol Architecture of the binary arithmetic Coder for UHDTV Video Encoders

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2020年第3期67卷 891-902页

作者： Pastuszak, Grzegorz Warsaw Univ Technol Inst Radioelect & Multimedia Technol PL-00661 Warsaw Poland

binary arithmetic coding is a key part of recent video compression standards. Its throughput is limited by the inherent dependencies existing in the algorithm. As a consequence, a higher bin parallelism leads to lower clock frequencies. This paper presents an architecture able to exceed limits existing in previous hardware implementations. The architecture exploits less probable symbols as starting points for long series of bins coded in one clock cycle. The evaluation for four possible cases of the range value allows its update in the pipeline before the delayed selection based on actual value. The adaptive division into series is proposed to make long series more frequent. To shorten critical paths, rMPS variables computed for symbols coded in the same clock cycle are first summed and then added to the low register. Up to 16 bypass-mode symbols can be processed in parallel with context-coded symbols in one clock cycle. The architecture is generative, i.e., its throughput can be scaled with resources without strict limits. For example, the binary arithmetic coder synthesized on 90nm TSMC technology which consumes 101.4k gates and operates at the 570 MHz has the average throughput of 13.4 bins per clock cycle for the high-quality H.265/HEVC compression.

关键词： CABAC binary arithmetic coding entropy coding video encoder VLSI FPGA UHDTV H264 AVC H265 HEVC

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Multisymbol Architecture of the Entropy Coder for H.265/HEVC Video Encoders

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2020年第12期28卷 2573-2583页

作者： Pastuszak, Grzegorz Warsaw Univ Technol Inst Radioelect & Multimedia Technol PL-00661 Warsaw Poland

In video compression, throughputs of entropy encoders based on arithmetic coding are limited. This article presents the architecture of the entropy coder able to process in each clock cycle much more binary symbols than previous works. The architecture takes advantage of the multisymbol implementation of the binary arithmetic coder (BAC) developed earlier. To balance high throughputs of the BAC, fast implementations of binarization, context modeling, and probability model (PM) update are developed. The main improvement in the symbol rate stems from the decomposition of the processing path into many parallel ones. Critical paths associated with state transitions are shortened since each path updates the PM only for one context selected in each clock cycle. The negative impact on the symbol rate is compensated by the context-based symbol reordering. Although paths have variable bin/symbol rates, the applied buffering strategy improves the continuity of two data streams directed to the BAC, separately for context-coded and bypass-mode symbols. The entropy coder synthesized for the 90-nm TSMC technology consumes 273-k gates and operates at 570 MHz. It achieves the average symbol rate of 13.08 bins per clock cycle and the throughput of 7455 Mbins/s for high-quality H.265/HEVC compression.

关键词： Entropy Throughput Clocks Streaming media Encoding Context modeling Multiplexing binary arithmetic coding entropy coding field-programmable gate array (FPGA) H265 HEVC UHDTV video compression

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A High-Throughput and Low-Complexity Decoding Scheme based on Logarithmic Domain

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JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2017年第3期88卷 245-257页

作者： Yu, Quanhe Yu, Wei Zheng, Jianhua Zheng, Xiaozhen He, Yun Rong, Yaocheng Tsinghua Univ Dept Elect Engn Rohm 10-201 Beijing 100084 Peoples R China HiSilicon Technol Co Ltd 156 Rd Beijing 100095 Peoples R China

This paper proposes a high-throughput and low-complexity decoder (D_LBAC) based on Logarithmic binary arithmetic coding (LBAC). It can easily implement multiple symbols decoding. The proposed scheme does not use multiplication and division operations nor look up tables (LUTs). It has a simple algorithm structure and only requires additions and shift operations. Experimental results show that it has about 0.2-0.7 % bit-rate savings and can decode 3.5 symbols per cycle on average. The hardware implementation design described in this paper can achieve a high symbol processing capability and the lower hardware costs.

关键词： binary arithmetic coding LBAC CABAC Entropy coding H.265/HEVC

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Application-Specific Cache and Prefetching for HEVC CABAC Decoding

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IEEE MULTIMEDIA 2017年第1期24卷 72-85页

作者： Habermann, Philipp Chi, Chi Ching Alvarez-Mesa, Mauricio Juurlink, Ben Tech Univ Berlin Embedded Syst Architecture Grp Berlin Germany Tech Univ Berlin Berlin Germany

Context-based Adaptive binary arithmetic coding (CABAC) is the entropy coding module in the HEVC/H.265 video coding standard. As in its predecessor, H.264/AVC, CABAC is a well-known throughput bottleneck due to its strong data dependencies. Besides other optimizations, the replacement of the context model memory by a smaller cache has been proposed for hardware decoders, resulting in an improved clock frequency. However, the effect of potential cache misses has not been properly evaluated. This work fills the gap by performing an extensive evaluation of different cache configurations. Furthermore, it demonstrates that application-specific context model prefetching can effectively reduce the miss rate and increase the overall performance. The best results are achieved with two cache lines consisting of four or eight context models. The 2 × 8 cache allows a performance improvement of 13.2 percent to 16.7 percent compared to a non-cached decoder due to a 17 percent higher clock frequency and highly effective prefetching. The proposed HEVC/H.265 CABAC decoder allows the decoding of high-quality Full HD videos in real-time using few hardware resources on a low-power FPGA.

关键词： Decoding Context Modeling Prefetching Syntactics Encoding binary arithmetic coding High Performance Computing HEVC H 265 CABAC Cache Prefetching Multimedia Hardware Embedded Systems

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An enhanced entropy coding scheme for HEVC

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SIGNAL PROCESSING-IMAGE COMMUNICATION 2016年 44卷 108-123页

作者： Gao, Min Fan, Xiaopeng Zhao, Debin Gao, Wen Harbin Inst Technol Dept Comp Sci & Technol Harbin 150001 Peoples R China Peking Univ Sch Elect Engn & Comp Sci Beijing 100000 Peoples R China

This paper presents a modification to Context-based Adaptive binary arithmetic coding (CABAC) in High Efficiency Video coding (HEVC), which includes an improved context modeling for transform coefficient levels and a binary arithmetic coding (BAC) engine with low memory requirement. In the improved context modeling for transform coefficient levels, the context model index for significance map is dependent on the number of the significant neighbors covered by a local template and its position within transform block (TB). To limit the total number of context models for significance map, TBs are split into different regions based on the coefficient position. The same region in different TBs shares the same context model set. For the first and second bins of the truncated unary scheme of absolute level minus one, their context model indices depend on the neighbors covered by a local template of the current transform coefficient level. Specifically, the context model index for the first bin is determined by the number of neighbors covered by the local template with absolute magnitude equal to 1 and larger than 1;for the second bin, its context model index is determined by the number of neighbors covered by the local template with absolute magnitude larger than 1 and larger than 2. Moreover, TB is also split into different regions to incorporate the coefficient position in the context modeling of the first bin in luma component. In the BAC engine with low memory requirement, the probability is estimated based on a multi-parameter probability update mechanism, in which the probability is updated with two different adaption speeds and use the average as the estimated probability for the next symbol. Moreover, a multiplication with low bit capacities is used in the coding interval subdivision to substitute the large look-up table to reduce its memory consumption. According to the experiments conducted on HM14.0 under HEVC main profile, the improved context modeling for trans

关键词： HEVC CABAC Entropy coding Context modeling binary arithmetic coding

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A High-Throughput binary arithmetic coding Architecture for H.264/AVC CABAC

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IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 2010年第9期E93A卷 1594-1604页

作者： Liu, Yizhong Song, Tian Shimamoto, Takashi Univ Tokushima Inst Sci & Technol Grad Sch Engn Tokushima 7708506 Japan

In this paper, we propose a high-throughput binary arithmetic coding architecture for CABAC (Context Adaptive binary arithmetic coding) which is one of the entropy coding tools used in the H.264/AVC main and high profiles. The full CABAC encoding functions, including binarization, context model selection, arithmetic encoding and bits generation, are implemented in this proposal. The binarization and context model selection are implemented in a proposed binarizer, in which a FIFO is used to pack the binarization results and output 4 bins in one clock. The arithmetic encoding and bits generation are implemented in a four-stage pipeline with the encoding ability of 4 bins/clock. In order to improve the processing speed, the context variables access and update for 4 bins are paralleled and the pipeline path is balanced. Also, because of the outstanding bits issue, a bits packing and generation strategy for 4 bins paralleled processing is proposed. After implemented in verilog-HDL and synthesized with Synopsys Design Compiler using 90 nm libraries, this proposal can work at the clock frequency of 250MHz and takes up about 58K standard cells, 3.2 Kbits register files and 27.6K bits ROM. The throughput of processing 1000 M bins per second can be achieved in this proposal for the HDTV applications.

关键词： H.264/AVC encoder CABAC entropy coding binary arithmetic coding VLSI

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A Highly Efficient VLSI Architecture for H.264/AVC Level 5.1 CABAC Decoder

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY 2012年第2期22卷 272-281页

作者： Liao, Yuan-Hsin Li, Gwo-Long Chang, Tian-Sheuan PixArt Imagine Inc Hsinchu 300 Taiwan Natl Chiao Tung Univ Dept Elect Engn Hsinchu 300 Taiwan

In this paper, a high throughput context-based adaptive binary arithmetic coding decoder design is proposed. This decoder employs a syntax element prediction method to solve pipeline hazard problems. It also uses a new hybrid memory two-symbol parallel decoding in order to enhance performance as well as to reduce costs. The critical path delay of the two-symbol binary arithmetic decoding engine is improved by 28% with an efficient mathematical transform. Experimental results show that the throughput of our proposed design can reach 485.76 Mbins/s in the high bit-rate coding and 446.2 Mbins/s on average at 264MHz operating frequency, which is sufficient to support H.264/AVC level 5.1 real-time decoding.

关键词： binary arithmetic coding CABAC entropy decoding H.264/AVC syntax parsing

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ECG Data Compression Using Wavelet Packet Technique on binary arithmetic coding 10th

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World Congress on Medical Physics and Biomedical Engineering

作者： Baig, Mirza Haris Sir Syed Univ Engn & Technol Karachi Siemens Med Solut Pakistan Karachi Pakistan

ISBN: (纸本)9783540368397

Electrocardiogram (ECG) coding is required in several applications such as ambulatory recording, patient data bases, medical education systems and ECG data transmission through communication channels. Digital storage media is not expensive in recent years, but increase in the need of ECG data in medical care there exists and imperative need to evolve effective compression techniques of ECG data. In general, the procedure of signal compress involves four steps: preprocessing, signal decomposition or transformation, quantization and coding. A new technique for ECG signal compression using wavelet packet transform (WPT) is presented in this paper. By applying the binary arithmetic coding on rearranged sparse information among subbands of quantized coefficient wavelet, we have obtained a compression ratio of more than 9 with PRD less than 4% for ECG signal extracted from MIT-BIH database.

关键词： ECG Compression Wavelet Packet Technique binary arithmetic coding

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