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Voltage Balancing for Bipolar DC Distribution Grids: A Power Flow Based binary integer Multi-Objective Optimization Approach

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IEEE TRANSACTIONS ON POWER SYSTEMS 2019年第1期34卷 28-39页

作者： Chew, Benjamin Si Hao Xu, Yan Wu, Qiuwei Nanyang Technol Univ Sch Elect & Elect Engn Singapore Singapore Tech Univ Denmark Dept Elect Engn Ctr Elect Power & Energy DK-2800 Lyngby Denmark Harvard Univ Sch Engn & Appl Sci Harvard China Project Cambridge MA 02138 USA

The re-emergence of two-phase bipolar dc distribution network, which utilizes the neutral wire for efficient distribution, has spurred research interest in recent years. In practice, system efficiency (power loss) and voltage unbalance are major concerns for the planning and design of the two-phase dc bipolar network. While most of the existing methodologies are power electronics solutions, there are very few works on resolving the problem from the power system perspective. This paper proposes amodel-based optimization method by first formulating the power flow model for two-phase dc bipolar network using the single line modeling technique and nodal analysis. Second, a binary integer load distribution model is proposed to consider the re-distribution of unipolar loads across the two unipolar distribution poles. Together with the power flow model, the system power loss and system voltage unbalance indices are formulated as a binary integer quadratic model. Third, a multi-objective optimization model is formulated and solved using the weighted sum approach. The proposed method is applied to a dc LED lighting system design, which considers both voltage unbalance and power loss. Using a 15 bus single source and a 33 bus multi-source network as case studies, the developed power flow model is validated with very high accuracy. Compared to existing iterative methods, the proposed model-based approach is able to significantly improve the voltage balancing across the distribution system.

关键词： 2-phase DC network modeling binary integer DC bipolar distribution system DC LED lighting system optimal load distribution voltage unbalance

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The use of fuzzy-weighted binary integer goal programming to select the optimum site for a central processing plant

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JOURNAL OF THE SOUTHERN AFRICAN INSTITUTE OF MINING AND METALLURGY 2017年第5期117卷 505-510页

作者： Bakhtavar, E. Khademi, D. Mikaeil, R. Urmia Univ Technol Dept Min & Mat Engn Orumiyeh Iran

Fuzzy-weighted integer goal programming has been developed and used to select the most suitable site to construct a central processing plant for several adjacent small-scale dimension stone quarries, based on the most effective criteria. In the first step of mathematical modelling, the most important goals and decision variables were defined. Accordingly, an objective function was used in the model for minimizing the sum of undesired fuzzy-weighted deviations. Fuzzy weights were determined by a matrix of pairwise comparisons of various expert judgments in this field and the fuzzy geometric mean. The goal and systemic constraints were also modelled. The most suitable site for the construction of the plant was selected after solving the mathematical model in the Excel (R) Solver add-in. The selected site had various advantages over the other sites, such as the shortest average distance to the quarries, the shortest distance to power access and workforce, and the lowest land price.

关键词： fuzzy multi-objective goal programming binary integer dimension stone quarry processing plant

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A SINGLE-CHIP IBM SYSTEM/390 FLOATING-POINT PROCESSOR IN CMOS

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IBM JOURNAL OF RESEARCH AND DEVELOPMENT 1992年第4期36卷 733-749页

作者： DAOTRONG, S HELWIG, K IBM Germany Schoenaicherstrasse 220 7030 Boeblingen Germany|c|

A floating-point processor with the IBM System/390(R) architecture is implemented in one CMOS VLSI chip containing over 70 000 cells (equivalent inverters), using a transistor channel length of 0.5 mum. All floating-point instructions are hard-wired, including the binary integer multiplications. The chip is implemented in a 1-mum technology with three layers of metal. All circuits are realized in standard cells except for a floating-point register and a multiplier array macro, which are custom designed to save chip area. Instructions are performed in a five-stage pipeline with a maximum operating frequency of 37 MHz. The chip measures 12.7 mm x 12.7 mm, and dissipates 2 W. It is part of the chip set which forms the core of the IBM Enterprise System/9000(TM) Type 9221 entry-level models.

关键词： .transistor data flow chip area inverters binary integer Enterprise System multiplier array floating-pointprocessor multiplier macro

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BIT SERIAL ADDITION TREES AND THEIR APPLICATIONS

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COMPUTING 1988年第1期40卷 9-17页

作者： MEIJER, H AKL, SG 1.Department of Computing and Information Science Queen's University K7L 3N6 Kingston Canada

Parallel algorithms are examined for a number of fundamental computational problems. All algorithms have as a basic operation the addition ofk-bit integers. For each problem we present a solution in the form of a logical circuit for which the product of the computation time and number of gates used is smaller than that of the best previously known algorithm.

关键词： B.5.1 [Register-Transfer-Level Implementation] Design-Arithmetic and logic units B.6.1 [Logic Design]: Design styles-Parallel circuits F.2.0. [Analysis of Algorithms and Problem Complexity]: General Algorithms Parallel algorithm logical circuit binary integer bit serial addition multiplication matrix multiplication selection sorting statistical computations

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ON THE BIT COMPLEXITY OF PARALLEL COMPUTATIONS

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INTEGRATION-THE VLSI JOURNAL 1988年第2期6卷 201-212页

作者： AKL, SG MEIJER, H Department of Computing and Information Science Queen's University Kingston Ontario Canada

The theoretical models of computation commonly used to design and analyze algorithms, whether sequential or parallel, usually assume that the word size is fixed and that the entire word is available at once. The purpose of this paper is to describe a number of architectures that are specifically designed to handle those situations where the conventional assumptions do not hold, i.e. where words can be arbitrarily long and/or their digits arrive serially. Four problems are considered: computing the sum of n k-bit integers, multiplying two k -bit integers, finding the partial sums of an array of n k -bit integers. Our solutions to these problems are all based on the concept of “on-the-fly” use of the input and intermediate result bits. For each architecture we present, the product of the solution time and the number of logical gates used is an improvement over that of any previously known circuit for the given problem that uses more than a constant number of processors.

关键词： Parallel algorithm logical circuit binary integer bit serial addition multiplication partial sums sorting

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