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Complete all-optical processing polarization-based binary logic gates and optical processors

OPTICS EXPRESS 2006年第21期14卷 9879-9895页

作者： Zaghloul, Y. A. Zaghloul, A. R. M. Georgia Inst Technol Sch Elect & Comp Engn Ellipsometry Res & Applicat Labs Savannah GA 31407 USA ITR Technol Inc Lincoln NE 68501 USA

We present a complete all-optical-processing polarization-based binary-logic system, by which any logic gate or processor can be implemented. Following the new polarization-based logic presented in [Opt. Express 14, 7253 (2006)], we develop a new parallel processing technique that allows for the creation of all-optical-processing gates that produce a unique output either logic 1 or 0 only once in a truth table, and those that do not. This representation allows for the implementation of simple unforced OR, AND, XOR, XNOR, inverter, and more importantly NAND and NOR gates that can be used independently to represent any Boolean expression or function. In addition, the concept of a generalized gate is presented which opens the door for reconfigurable optical processors and programmable optical logic gates. Furthermore, the new design is completely compatible with the old one presented in [Opt. Express 14, 7253 (2006)], and with current semiconductor based devices. The gates can be cascaded, where the information is always on the laser beam. The polarization of the beam, and not its intensity, carries the information. The new methodology allows for the creation of multiple-input-multiple-output processors that implement, by itself, any Boolean function, such as specialized or non-specialized microprocessors. Three all-optical architectures are presented: orthoparallel optical logic architecture for all known and unknown binary gates, single-branch architecture for only XOR and XNOR gates, and the railroad (RR) architecture for polarization optical processors (POP). All the control inputs are applied simultaneously leading to a single time lag which leads to a very-fast and glitch-immune POP. A simple and easy-to-follow step-by-step algorithm is provided for the POP, and design reduction methodologies are briefly discussed. The algorithm lends itself systematically to software programming and computer-assisted design. As examples, designs of all binary gates, multiple-inp

关键词： .always produce represent truth cascaded laser beam Boolean unforced optical logic binary logic optical processors generalized gate carries orthoparallel binary gates XOR and XNOR

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Unforced polarization-based optical implementation of binary logic

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OPTICS EXPRESS 2006年第16期14卷 7252-7269页

作者： Zaghloul, Y. A. Zaghloul, A. R. M. Georgia Inst Technol Sch Elect & Comp Engn Ellipsometry Res Lab Savannah GA 31407 USA Georgia Inst Technol Sch Elect & Comp Engn Applicat Lab Savannah GA 31407 USA ITR Technol Inc Lincoln NE 68501 USA

We preset a new method to optically represent and implement binary logic, and we implement some unforced logic gates. The binary logic zero and one are taken to be an optical beam, or any electromagnetic wave, that is polarized at a selected state and its negation, orthogonal counterpart, or otherwise. In one implementation, a thin-film system is then designed and used so as it can move between 2 positions producing the net desired polarization change of the output. The output consists of a wave that is polarized either in the direction of the original logic 1 or 0 or any other chosen state and its negation, orthogonal counterpart. The system can be cascaded infinitely due to the fact that the output and input are both of the same format and that the logic zero and one are not dependant on the intensity of the input or the output light beam. The unforced gates exclusive OR and exclusive NOR along with a simple inverter are demonstrated in this communication. We present three design architectures, where each has two types of gates. In one type of gates the polarization state magnitude can carry information that can be employed for testability or reverse logic. XOR, XNOR, and inverter gate designs and operation are discussed in detail, and an easy-to-follow step-by-step algorithm is presented. The introduced architectures are easily adapted for simultaneous cascading, multiple input designs, and integrated optical architecture. * Patent Pending (c) 2006 Optical Society of America.

关键词： .magnitude represent Electromagnetic Wave Simultaneous cascaded thin-film implement producing logic gates Cascading polarization state XOR light beam unforced XNOR binary logic

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MULTIPLICATIVE ALGORITHMS FOR TERNARY ARITHMETIC USING binary logic

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IEEE TRANSACTIONS ON COMPUTERS 1977年第8期26卷 823-826页

作者： BARAK, AB HEBREW UNIV JERUSALEM DEPT COMP SCIJERUSALEM 91000ISRAEL

This correspondence describes three algorithms of multiplicative type for ternary (base three) arithmetic using binary logic. The algorithms that are developed are multiplication, division, and natural logarithms. The... 详细信息

关键词： Arithmetics binary logic normalization method recursion algorithms ternary arithmetics.

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The binary logic of the Compilation of the Ecological Environment Code and Its Unfolding

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Social Sciences in China 2024年第3期45卷 76-94页

作者： Dou Xiaodong Guanghua Law School Zhejiang University

The Ecological Environment Code,as a significant legal instrument for the evolution of ecological civilization,possesses both substantive and formal ***,it aims to serve the national ecological civilization ***,it elucidates potential pathways for legal interpretation,development of legal rules,and promotion of judicial governance,restraining arbitrary behavior and disorder while facilitating systemic *** compilation of the Ecological Environment Code unfolds through the main threads of substantive and formal *** prioritizing conservation,protection,and restoring the natural environment,resource management,pollution prevention,and ecological protection are coordinated,integrating legislation on ecological protection with management of natural resources and pollution prevention to achieve both"harm avoidance"and"beneficial trends."Employing the formal logical main thread of the structure of the relationship between power and rights,we present four types of norms:ex post facto remedy,hazard prevention,risk prevention,and independent value selection.

关键词： compilation of the Ecological Environment Code binary logic main thread of formal logic main thread of substantive logic

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Processing binary and Fuzzy logic by Chaotic Time Series Generated by a Hydrodynamic Photochemical Oscillator

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CHEMPHYSCHEM 2017年第13期18卷 1831-1841页

作者： Gentili, Pier Luigi Giubila, Maria Sole Heron, B. Mark Univ Perugia Dept Chem Biol & Biotechnol I-06123 Perugia Italy Univ Huddersfield Sch Appl Sci Dept Chem & Biol Sci Huddersfield HD1 3DH W Yorkshire England

This work demonstrates the computational power of a hydrodynamic photochemical oscillator based on a photochromic naphthopyran generating aperiodic time series. The chaotic character of the time series is tested by calculating its largest Lyapunov exponent and the correlation dimension of its attractor after building its phase space through the Takens' theorem. Then, the chaotic dynamic is shown to be suitable to implement all the fundamental Boolean two-inputs-one-output logic gates. Finally, the strategy to implement fuzzy logic systems (FLSs) based on the time series is described. Such FLSs promise to be useful in the field of computational linguistics, which is concerned with the development of artificial intelligent systems able to transform collections of numerical data into natural language texts.

关键词： binary logic chaos computing fuzzy logic photochemistry photochromism

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Asynchronous Linear Combinational Circuits as a Base for Programmable logic Device. binary and Ternary Cases

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IFAC-PapersOnLine 2016年第25期49卷 378-383页

作者： Latypov, Rustam Kh. Stolov, Evgeni L. Kazan Federal University Kazan420008 Russia

Programmable logic devices on base of asynchronous combinational circuits with feedback are considered. The main aim of the research is to obtain a method for designing a circuit with a set of prescribed stable states or a circuit without stable states — a generator of true random numbers. Both the cases of binary and ternary logics are studied. © 2016

关键词： Computer circuits Feedback Linear networks logic devices Programmable logic controllers Random number generation Timing circuits binary logic Linear circuits Programmable logic device Stable state Ternary logic True randoms

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Asynchronous Linear Combinational Circuits as a Base for Programmable logic Device. binary and Ternary Cases

Asynchronous Linear Combinational Circuits as a Base for Pro...

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14th IFAC Conference on Programmable Devices and Embedded Systems (PDES)

作者： Latypov, Rustam Kh. Stolov, Evgeni L. Kazan Fed Univ Kazan 420008 Russia

Programmable logic devices on base of asynclrronous combinational circuits with feedback are considered. The main aim of the research is to obtain a method for designing a circuit with a set of prescribed stable states or a circuit without stable states a generator of true random numbers. Both the cases of binary and ternary logics are studied. (C) 2016, IFAC (International Federation of Automatic Control) Hosting by Elsevier Ltd. All rights reserved.

关键词： programmable logic device asynchronous linear circuit feedback ternary logic binary logic

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Multi-valued logic design methodology with double negative differential resistance transistors

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MICRO & NANO LETTERS 2017年第10期12卷 738-743页

作者： Ji, Yuchao Chang, Sheng Wang, Hao Huang, Qijun He, Jin Yi, Fan Wuhan Univ Sch Phys & Technol Key Lab Acoust & Photon Mat & Devices Minist Educ Wuhan 430072 Hubei Peoples R China Wuhan Donghu Univ Sch Elect & Informat Engn Wuhan 430212 Hubei Peoples R China

Multi-valued logic (MVL) is one of the promising alternatives of binary logic since it has a high-logic density, which brings a vision of simpler circuit structure. Based on a novel concept as double negative differential resistance field effect transistor and its analytic description, a design methodology utilising the mechanism of monostable-to-multistable transition logic element (MMLE) for MVL is proposed in this study. The basic ternary logic gates are designed as a complete logic set, and a compact ternary four-input full adder is constructed as an example of function circuits. Comparing with binary circuit and ternary circuit based on conventional design, the circuit shows advantage in device cost and other properties. The results verify that this MMLE design methodology has a good information load ability, which will have a brilliant prospect in MVL circuits.

关键词： logic gates negative resistance circuits field effect transistors adders multivalued logic design methodology binary logic logic density circuit structure double negative differential resistance field effect transistor monostable-multistable transition logic element MMLE MVL ternary logic gates ternary four-input full adder function circuits binary circuit ternary circuit information load ability

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Design of ternary logic gates and circuits using GNRFETs

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IET CIRCUITS DEVICES & SYSTEMS 2020年第7期14卷 972-979页

作者： Madhuri, Badugu Divya Sunithamani, Subramani Koneru Lakshmaiah Educ Fdn Elect & Commun Engn Dept Guntur 522502 Andhra Pradesh India

In this study, the design of digital logic gates and circuits in ternary logic is presented. The ternary logic is observed to be a better alternative to the traditional binary logic because it offers faster computations, smaller chip area, and lesser interconnects. Thus, it allows designing the low-complex, high-speed, and energy-efficient circuits in future digital design. A novel technique is proposed to design the ternary logic gates using multi-threshold graphene nanoribbon field-effect transistors (GNRFETs). The GNRFET threshold voltage is controlled by the width of the graphene nanoribbon, which is defined by the dimer lines number. Three different inverters are designed namely standard, positive, and negative inverters along with the basic and universal logic gates. Additionally, the ternary half adder and full adder are proposed that further helps to design the complex arithmetic circuits. All the proposed ternary logic circuits have been extensively simulated in SPICE for functional verification and performance analysis. The performance of the proposed ternary logic circuits is compared with the existing designs presented in the literature. The comparison results show that the propagation delay and circuit area of GNRFET-based circuits are reduced with an average of 41.3 and 64%, respectively, than the existing ternary circuits.

关键词： ternary logic adders logic gates nanoribbons nanoelectronics field effect transistors logic design logic circuits SPICE graphene devices ternary logic gates digital logic gates binary logic low-complex speed energy-efficient circuits digital design multithreshold graphene nanoribbon field-effect transistors basic logic gates universal logic gates ternary half adder complex arithmetic circuits ternary logic circuits propagation delay GNRFET-based circuits low-complex circuits high-speed circuits GNRFET threshold voltage control SPICE functional verification C

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Ternary DDCVSL: a combined dynamic logic style for standard ternary logic with single power source

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IET COMPUTERS AND DIGITAL TECHNIQUES 2020年第4期14卷 166-175页

作者： Azimi, Nooshin Mirzaee, Reza Faghih Navi, Keivan Rahmani, Amir Masoud Islamic Azad Univ Dept Comp Engn Sci & Res Branch Tehran Iran Islamic Azad Univ Dept Comp Engn Shahr E Qods Branch Tehran Iran Shahid Beheshti Univ Fac Elect & Comp Engn GC Tehran Iran

Every logic style has certain advantages for a specific application. Therefore, it is essential to introduce and investigate different logic styles. Differential cascode voltage switch logic (DCVSL) with the inherent redundancy is known to be an ideal logic style for error detection applications. This study combines ternary static DCVSL (SDCVSL) with dynamic logic (DL) to realise ternary dynamic DCVSL (DDCVSL) by means of a single power source. At first, it is shown that why the same static-to-dynamic conversion method in binary logic fails to operate correctly in ternary logic. Then, two solutions are given. Static power dissipation and switching activity are particularly dealt with in the second proposed ternary DDCVSL to reduce power consumption. The new designs are simulated and tested by using HSPICE simulator and 32 nm Stanford carbon nanotube field effect transistor model. Simulation results and comparisons with a vast range of conventional and state-of-the-art competitors show prominence and great potential for the new ternary circuit methodology. For example, the authors second proposed ternary DDCVSL AND/NAND has 19.7, 37.4, and 60.5% higher performance than some famous static ternary logic styles such as CMOS-like, SDCVSL, and pseudo N-type, respectively, in terms of energy consumption.

关键词： logic gates logic design logic circuits ternary logic low-power electronics carbon nanotube field effect transistors field effect transistor circuits redundancy combined dynamic logic style standard ternary logic single power source differential cascode voltage switch logic ideal logic style error detection applications ternary static DCVSL ternary dynamic DCVSL static-to-dynamic conversion method binary logic static power dissipation power consumption ternary circuit methodology Stanford carbon nanotube field effect transistor model static ternary logic styles SDCVSL switching activity HSPICE simulator ternary DDCVSL AND-NAND energy consumption size 32 0 nm

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