检索结果-内蒙古大学图书馆

Low Power VLSI architectures for One Bit Transformation Based Fast motion estimation

IEEE TRANSACTIONS ON CONSUMER ELECTRONICS 2010年第4期56卷 2652-2660页

作者： Chatterjee, Sumit K. Chakrabarti, Indrajit Indian Inst Technol Dept Elect & Elect Commun Engn Kharagpur 721302 W Bengal India

In the present paper, architectures implementing fixed block size and variable block size (VBS) motion estimation ( ME) algorithms on one bit transformed (1-BT) image frames have been presented. The proposed architectures perform ME by applying diamond search (DS) algorithm on 1-BT image frames. The 1-BT based ME is usually performed by applying full search (FS) algorithm. Our simulation results reveal that the application of DS on 1-BT based ME can significantly reduce the computational complexity which is observed in FS based 1-BT ME at a tolerable degradation in the quality. In terms of latency, the architectures have been shown to be superior to several other 1-BT ME architectures. The presented DS based 1-BT ME architectures have succeeded in reducing the minimum clock frequency required to process a video sequence with a given frame size and frame rate, which in turn reduces the overall power consumption compared with other ME architectures. In particular, for processing SDTV sequences (1280x720 @ 30 fps), the power consumption by the proposed VBS ME architecture is reduced by at least 41% compared to the other 1-BT based ME architectures available in literature. The proposed architectures are therefore, considered suitable for low-power portable video applications typically operated by battery power(1).

关键词： One bit transformation binary motion estimation architecture data reuse diamond search algorithm low power design variable block size

来源：评论

学校读者我要写书评

暂无评论

Implementation of Weighted Constrained One-Bit Transformation Based Fast motion estimation

引用

IEEE TRANSACTIONS ON CONSUMER ELECTRONICS 2012年第2期58卷 646-653页

作者： Chatterjee, Sumit K. Asansol Engn Coll Dept Elect & Commun Engn Asansol 713104 India

An efficient architecture that implements motion estimation based on a combination of diamond search algorithm and weighted constrained one-bit transformation is presented. The component of any motion estimation hardware that deals with the memory access consumes considerable power. This paper reports efforts at exploiting the overlap of search data among various search locations to reduce the number of memory accesses. The proposed architecture can reduce total power consumption by up to 23% compared to a recently reported architecture. Moreover, only 9 processing elements are used in this architecture, as against 16 processing elements used in conventional one bit transformation based motion estimation hardware. This in turn substantially reduces the total area of the architecture. As the proposed architecture is area efficient in addition to consuming relatively less power, its potential application lies in portable consumer video playback systems typically operated by batteries.

关键词： One bit transformation binary motion estimation architecture weighted constrained one-bit transform

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：