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An FPGA-based binary neural network accelerator with enhanced hardware efficiency and data reuse

MICROELECTRONICS JOURNAL 2025年 156卷

作者： Zhang, Dezheng Cen, Rui Pu, Han Wan, Rui Wang, Dong Beijing Jiaotong Univ Inst Informat Sci Beijing 100044 Peoples R China Network Technol Beijing Key Lab Adv Informat Sci Beijing 100044 Peoples R China Tiangong Univ Sch Comp Sci & Technol Tianjin 300387 Peoples R China

binary neural network (BNN) algorithms have gained significant attention due to their low computational complexity and improved accuracy. Field-programmable gate array (FPGA)-based accelerators for BNNs typically transform binary operations into XNOR and popcount operations, efficiently utilizing logic resources. However, fixed-point operations in the first and final layers result in high hardware costs. Moreover, frequent off-chip memory access, particularly for shortcut operations, can severely limit throughput. This paper introduces a hardware-efficient FPGA-based BNN accelerator with minimized off-chip memory access. The first layer's inputs are binarized using an enhanced thermometer encoding scheme, enabling all convolution layers to be executed on a unified binary computing unit. A multi-mode computing unit is designed to perform both ReAct parametric rectified linear unit (RPReLU) and linear operations using shared hardware multipliers, which maximizes hardware reuse. To address bandwidth limitations, we implement a dynamic data buffering architecture, featuring high-bandwidth and high-volume buffers for caching intra-layer and cross-layer data, respectively. The accelerator supports two data buffering schemes, and the one minimizing the off-chip memory access is selected for each convolution layer. The accelerator is evaluated on an Alinx AXU3EGB development board and a custom development board with a Xilinx XC7V690T device, respectively. Experiments on ImageNet demonstrate 69.34% accuracy, with frames per second (FPS) of 129.1 and 405.6 on the ZU3EG and XC7V690T devices, respectively. Compared to the state-of-the-art design, our accelerator achieves 2.7x FPS on the same FPGA device.

关键词： binary neural network FPGA circuit design Accelerated computing High-level synthesis (HLS)

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Mechanical fault diagnosis method based on binary neural network with adaptive depth-to-width ratio

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MEASUREMENT SCIENCE AND TECHNOLOGY 2025年第4期36卷 046104-046104页

作者： Liu, Chenyu Li, Zhinong Wang, Fengtao Li, Zhe Yang, Wenxian Nanchang Hangkong Univ Key Lab Nondestruct Testing Minist Educ Nanchang 330063 Peoples R China Shantou Univ Key Lab Intelligent Mfg Technol Minist Educ Shantou 515063 Peoples R China AECC Shenyang Liming Aeroengine Co Ltd Shenyang 110043 Peoples R China Univ Huddersfield Sch Comp & Engn Huddersfield HD1 3DH England

Deep neural network (DNN) has powerful feature extraction and classification abilities and is extensively used in mechanical fault diagnosis. However, in the DNN-based fault diagnosis method, too many model parameters, high computational complexity, and occupying a large amount of storage space make it very difficult to optimize and retrain the DNN model. To overcome this deficiency, a binary neural network (BNN) is introduced into fault diagnosis. In the proposed BNN-based fault diagnosis method, the floating-point weights and activations are binarized as '+1' and '-1' to save storage space, and the floating-point multiply-accumulate operations (OPs) are replaced by bitwise OPs to reduce the computational complexity. The BNN-based fault diagnosis method effectively compresses the structure of DNNs and accelerates model inference. However, the binarization OP may bring about the quantization error and gradient error, which will accumulate with the increase of the network depth, and lead to a degradation in model performance. To solve these deficiencies in the proposed BNN-based fault diagnosis method, an improved BNN fault diagnosis method based on adaptive depth-to-width ratio (ADTWR) is proposed. For the convenience in description, the proposed method is called the BNN-ADTWR method. In the proposed BNN-ADTWR method, the network structure is reshaped by the comparison of the gains brought by the depth and width of the backbone network, and the backbone network is further optimized by the pruning technique. To evaluate the effectiveness of the proposed method, the comparative experiments, such as ablation, anti-noise, and computational complexity, had successfully completed on several rolling bearing datasets. The experiment results show that the proposed BNN-ADTWR method significantly reduces computational complexity and helps with rapid fault diagnosis. The constructed ADTWR backbone network decreases activations in the traditional backbone network and improves ab

关键词： fault diagnosis deep neural network binary neural network adaptive depth-to-width ratio

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binary neural-network WITH NEGATIVE SELF-FEEDBACK AND ITS APPLICATION TO N-QUEENS PROBLEM

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IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS 1994年第4期E77D卷 459-465页

作者： OHTA, M OGIHARA, A FUKUNAGA, K Univ of Osaka Prefecture Sakai-shi Japan

This article deals with the binary neural network with negative self-feedback connections as a method for solving combinatorial optimization problems. Although the binary neural network has a high convergence speed, it hardly searches out the optimum solution, because the neuron is selected randomly at each state update. In this article, an improvement using the negative self-feedback is proposed. First it is shown that the negative self-feedback can make some local minimums be unstable. Second a selection rule is proposed and its property is analyzed in detail. In the binary neural network with negative self-feedback, this selection rule is effective to escape a local minimum. In order to confirm the effectiveness of this selection rule, some computer simulations are carried out for the N-Queens problem. For N = 256, the network is not caught in any local minimum and provides the optimum solution within 2654 steps (about 10 minutes).

关键词： binary neural network NEGATIVE SELF-FEEDBACK CONNECTION SELECTION RULE N-QUEENS PROBLEM

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binary neural network Aided CSI Feedback in Massive MIMO System

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IEEE WIRELESS COMMUNICATIONS LETTERS 2021年第6期10卷 1305-1308页

作者： Lu, Zhilin Wang, Jintao Song, Jian Tsinghua Univ Dept Elect Engn Beijing 100084 Peoples R China Tsinghua Univ Beijing Natl Res Ctr Informat Sci & Technol BNRis Beijing 100084 Peoples R China

In massive multiple-input multiple-output (MIMO) system, channel state information (CSI) is essential for the base station (BS) to achieve high performance gain. The CSI matrix needs to be estimated and fed back from user equipment (UE) in frequency division duplexing (FDD) mode. Recently, deep learning is widely used in CSI compression to reduce the feedback overhead. However, applying neural network brings extra memory and computation cost, which is non-negligible especially for the resource limited UE. In this letter, a novel binarization aided feedback network named BCsiNet is introduced to lighten the encoder at UE. The proposed BCsiNet offers over 30x memory saving and around 2x inference acceleration for the encoder compared with CsiNet. Moreover, experiments show that the feedback performance of BCsiNet can be comparable with original CsiNet even with the encoder binarized.

关键词： Massive MIMO CSI feedback deep learning binary neural network lightweight network

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binary neural network with P4 on Programmable Data Plane 18

Binary Neural Network with P4 on Programmable Data Plane

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18th IEEE International Conference on Mobility, Sensing and networking (MSN)

作者： Luo, Junming Liu, Waixi Tan, Miaoquan Chen, Haosen Guangzhou Univ Sch Elect & Commun Engn Guangzhou 510006 Peoples R China

ISBN: (纸本)9781665464574

Deploying machine learning (ML) on the programmable data plane (PDP) has some unique advantages, such as quickly responding to network dynamics. However, compared to demands of ML, PDP have limited operations, computing and memory resources. Thus, some works only deploy simple traditional ML approaches (e.g., decision tree, K-means) on PDP, but their performance is not satisfactory. In this article, we propose P4-BNN (binary neural network based on P4), which uses P4 to completely executes binary neural network on PDP. P4-BNN addresses some challenges. First, in order to use shift and simple integer arithmetic operations to replace multiplication, P4-BNN proposes a tailor-made data structure. Second, we use an equivalent replacement programming method to support matrix operation required by ML. Third, we propose a normalization method in PDP which needn't floating-point operations. Fourth, by using register storing the model parameters, the weights of P4-BNN model can be updated without interrupting the P4 program running. Finally, as two use-cases, we deploy P4-BNN on a Netronome SmartNIC (Agilio CX 2x10GbE) to achieve flow classification and anomaly detection. Compared to the N3IC, decision tree and K-means, the accuracy of P4-BNN has 1.7%, 3.4% and 47.7% improvement respectively.

关键词： binary neural network P4 Programmable Data Plane anomaly detection flow classification

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binary neural network based real time emotion detection on an edge computing device to detect passenger anomaly 34

Binary neural network based real time emotion detection on a...

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34th International Conference on VLSI Design / 20th International Conference on Embedded Systems (VLSID)

作者： Ajay, B. S. Rao, Madhav Intel Technol India Pvt Ltd Bangalore Karnataka India Int Inst Informat Technol Surg & Assist Robot Lab Bangalore Karnataka India

ISBN: (纸本)9781665440875

Passenger safety in public transportation especially while riding in the form of shared cabs, and taxis are often ignored, and not much preventive protocols are devised. In the connected mobility world, emotion recognition from facial expressions is a possibility, however a faster processing and edge computing device to derive anomaly state inferences will be apt for further notifying about the safety of the passenger. FPGA implementation is a viable approach to not only implement in the embedded system automotive electronics, but also accelerate the inference results, hence making it as an ideal real time candidate for passenger anomaly state identification. For the same, a real time emotion detection system using facial features was implemented on FPGA. A binary neural network (BNN) feeded by Local binary Pattern (LBP) output was designed towards the development of an improved and faster emotion recognition system. LBP is configured as a preprocessing step to extract facial features that is passed on to the BNN layer for successful inference. The preprocessing method utilizes Viola-Jones (VJ) algorithm to extract facial data while removing other background information from the image. The LBP-BNN network is modelled using Facial Expression 2013 (FER-2013) data set for training. The custom hardware accelerator or the overlay is synthesized and the designed IP is implemented on FPGA for the inference. Inference is done using the trained model on FPGA to enable faster classified results. Emotion detection using facial expressions is classified to six states namely: angry, disgust, fear, happy, sad, and surprise. The LBP-BNN network is implemented in FPGA, to realize a real time facial emotion recognition by capturing the image of a person from a web camera interfaced to the FPGA acting as edge computing inference device, with acceptable accuracy. The image processing based emotion detection design is highly suitable for other applications including tracking of emotion

关键词： Facial emotion recognition binary neural network hardware accelerator FPGA system design

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binary neural network for Video Action Recognition 29th

Binary Neural Network for Video Action Recognition

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29th International Conference on MultiMedia Modeling (MMM)

作者： Han, Hongfeng Lu, Zhiwu Wen, Ji-Rong Renmin Univ China Sch Informat Beijing Peoples R China Renmin Univ China Gaoling Sch Artificial Intelligence Beijing Peoples R China Beijing Key Lab Big Data Management & Anal Method Beijing Peoples R China

ISBN: (纸本)9783031270765;9783031270772

In the typical video action classification scenario, it is critical to extract the temporal-spatial information in the videos with complex 3D convolution neural networks, which significantly expand both the computation cost and memory costs. In this paper, we propose a novel 1-bit 3D convolution block named 3D BitConv, capable of compressing the 3D convolutional networks while maintaining a high level of accuracy. Due to its high flexibility, the proposed 3D BitConv block can be directly embedded in the latest 3D convolutional backbone. Consequently, we binarize two representative 3D convolutional neural networks (C3D and ResNet3D) and validate the accuracy of action recognition tasks. The results of two widely used datasets demonstrate that the two proposed binary 3D networks achieve impressive performance at a lower cost. Furthermore, we carry out an extensive ablation analysis to test and verify the efficacy of the components in 3D BitConv.

关键词： binary neural network Action recognition 1-bit 3D convolution

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A 3D MCAM architecture based on flash memory enabling binary neural network computing for edge AI

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Science China(Information Sciences) 2024年第12期67卷 302-310页

作者： Maoying BAI Shuhao WU Hai WANG Hua WANG Yang FENG Yueran QI Chengcheng WANG Zheng CHAI Tai MIN Jixuan WU Xuepeng ZHAN Jiezhi CHEN School of Information Science and Engineering Shandong University Center for Spintronic and Quantum Systems State Key Laboratory for Mechanical Behavior of MaterialsSchool of Materials Science and Engineering Xi'an Jiaotong University

The in-memory computing(IMC) architecture implemented by non-volatile memory units shows great possibilities to break the traditional von Neumann bottleneck. In this paper, a 3D IMC architecture is proposed whose unit is based on a multi-bit content-addressable memory(MCAM). The MCAM unit is comprised of two 65 nm flash memory and two transistors(2Flash2T), which is reconfigurable and multifunctional for both data write/search and XNOR logic operation. Moreover, the MCAM array can also support the population count(POPCOUNT) operation, which can be beneficial for the training and inference process in binary neural network(BNN) computing. Based on the well-known MNIST dataset, the proposed 3D MCAM architecture shows a 98.63% recognition accuracy and a 300% noise-tolerant performance without significant accuracy deterioration. Our findings can provide the potential for developing highly energy-efficient BNN computing for complex artificial intelligence(AI) tasks based on flash-based MCAM units.

关键词： reconfigurable multifunction multi-bit content-addressable memory (MCAM) bitwise operation binary neural network edge AI flash memory in-memory computing (IMC)

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FlexBNN: Fast Private binary neural network Inference With Flexible Bit-Width

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IEEE TRANSACTIONS ON INFORMATION FORENSICS AND SECURITY 2023年 18卷 2382-2397页

作者： Dong, Ye Chen, Xiaojun Song, Xiangfu Li, Kaiyun Chinese Acad Sci Inst Informat Engn Beijing 100045 Peoples R China Natl Univ Singapore Sch Comp Singapore 119077 Singapore

Advancements in deep learning enable neural network (NN) inference to be a service, but service providers and clients want to keep their inputs secret for privacy protection. Private Inference is the task of evaluating NN without leaking private inputs. Existing secure multiparty computation (MPC)based solutions mainly focus on fixed bit-width methodology, such as 32 and 64 bits. binary neural network (BNN) is efficient when evaluated in MPC and has achieved reasonable accuracy for commonly used datasets, but prior private BNN inference solutions, which focus on Boolean Circuits, are still costly in communication and run-time. In this paper, we introduce FLEXBNN, a fast private BNN inference framework using three-party computation (3PC) in Arithmetic Circuits against semi-honest adversaries with honest-majority. In FLEXBNN, we propose to employ flexible and small bit-width equipped with a seamless bit-width conversion method and design several specific optimizations towards the basic operations: i) We propose bit-width determination methods for Matrix Multiplication and Sign-based Activation function. ii) We integrate Batch Normalization and Max-Pooling into the Sign-based Activation function for better efficiency. iii) More importantly, we achieve seamless bit-width conversion within the Sign-based Activation function with no additional cost. Extensive experiments illustrate that FLEXBNN outperforms stateof-the-art solutions in communication, run-time, and scalability. On average, FLEXBNN is 11x faster than XONN (USENIX Security'19) in LAN, 46x (resp. 9.3x) faster than QUOTIENT (ACM CCS'19) in LAN (resp. WAN), 10x faster than BANNERS (ACM IH&MMSec'21) in LAN, and 1.1-2.9x (resp. 1.5-2.7x) faster than FALCON (semi-honest, PoPETs'21) in LAN (resp. WAN), and improves the respective communication by 500x, 127x, and 1.3-1.5x compared to XONN, BANNERS, and FALCON.

关键词： Cryptography Protocols Local area networks Artificial neural networks Arithmetic Costs Optimization Secure multiparty computation privacy-preserving deep learning binary neural network

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StereoEngine: An FPGA-Based Accelerator for Real-Time High-Quality Stereo Estimation With binary neural network

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2020年第11期39卷 4179-4190页

作者： Chen, Gang Ling, Yehua He, Tao Meng, Haitao He, Shengyu Zhang, Yu Huang, Kai Sun Yat Sen Univ Sch Data & Comp Sci Guangzhou 510275 Peoples R China Northeastern Univ Sch Comp Sci & Engn Shenyang Peoples R China

Stereo estimation is essential to many applications such as mobile autonomous robots, most of which ask for real-time response, high energy, and storage efficiency. Deep neural networks (DNNs) have shown to yield significant gains in improving accuracy. However, these DNN-based algorithms are challenging to be deployed on energy and resource-constrained devices due to the high computational complexities of DNNs. In this article, we present StereoEngine, a fully pipelined end-to-end stereo vision accelerator that computes accurate dense depth in a real-time and energy-efficient manner. An efficient stereo algorithm is developed and optimized for a high-quality hardware-friendly implementation, that leverages binary neural network (BNN) to learn discriminative binary descriptors to improve the disparity. The design of StereoEngine is a standalone DNN-based stereo vision system where all processing procedures are implemented on a hardware platform. The effectiveness of StereoEngine is evaluated by comprehensive experiments. Compared with software-based implementations on the high-end and embedded Nvidia GPUs, StereoEngine achieves up to 3x, 13x, and 50x speedups, as well as up to 211x, 58x, and 73x energy efficiency improvement, respectively. Furthermore, StereoEngine achieves leading accuracy when compared to state-of-the-art hardware implementations on the challenging KITTI dataset.

关键词： binary neural network FPGA accelerator high-quality stereo estimation real-time

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