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INTERACTIVE GROUP DECISION-MAKING USING FUZZY-PROGRAMMING WITH PREFERENCE CRITERIA

FUZZY SETS AND SYSTEMS 1992年第1期45卷 13-23页

作者： TAPIA, CG MURTAGH, BA School of Mechanical and Industrial Engineering University of New South Wales P.O. Box 1 Kensington N.S.W. Australia 2033

This paper presents an algorithm for solving a decision situation involving many decision-makers who are all concerned with determining a compromise solution to a given multiobjective problem. Fuzzy programming enables the decision-makers to vary, at any given iteration in the execution of a computer programme, their fuzzy aspiration levels in terms of input information known as preference criteria and underachievement tolerance values. Since conflict in aspiration levels usually entails an infeasible situation, a binary search technique is applied to the set of aspiration levels until a feasible efficient and acceptable compromise solution is obtained.

关键词： INTERACTIVE MULTICRITERIA ANALYSIS ASPIRATION-ORIENTED GROUP DECISION-MAKING NONLINEAR OR LINEAR FUZZY MATHEMATICAL PROGRAMMING MEMBERSHIP FUNCTIONS binary search algorithm

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A 515 nW, 0-18 dB Programmable Gain Analog-to-Digital Converter for In-Channel Neural Recording Interfaces

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IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS 2014年第3期8卷 358-370页

作者： Rodriguez-Perez, Alberto Delgado-Restituto, Manuel Medeiro, Fernando Inst Microelect Seville Seville 41092 Spain

This paper presents a low-area low-power Switched-Capacitor (SC)-based Programmable-Gain Analog-to-Digital Converter (PG-ADC) suitable for in-channel neural recording applications. The PG-ADC uses a novel implementation of the binary search algorithm that is complemented with adaptive biasing techniques for power saving. It has been fabricated in a standard CMOS 130 nm technology and only occupies 0.0326 mm(2). The PG-ADC has been optimized to operate under two different sampling modes, 27 kS/s and 90 kS/s. The former is tailored for raw data conversion of neural activity, whereas the latter is used for the on-the-fly feature extraction of neural spikes. Experimental results show that, under a voltage supply of 1.2 V, the PG-ADC obtains an ENOB of 7.56 bit (8-bit output) for both sampling modes, regardless of the gain setting. The amplification gain can be programmed from 0 to 18 dB. The power consumption of the PG-ADC at 90 kS/s is 1.52 mu W with a FoM of 89.49 fJ/conv, whereas at 27 kS/s it consumes 515 nW and obtains a FoM of 98.31 fJ/conv.

关键词： Analog-to-digital converter (ADC) binary search algorithm biomedical low-power low-voltage mismatch programmable gain amplifier (PGA) successive approximation switched-capacitor (SC) circuits

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Intelligent Multicriteria Decision Support System for Systems Design

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JOURNAL OF AIRCRAFT 2014年第1期51卷 216-225页

作者： Sun, Xiaoqian Gollnick, Volker Li, Yongchang Stumpf, Eike German Aerosp Ctr DLR Inst Air Transportat Syst D-21079 Hamburg Germany Georgia Inst Technol Sch Aerosp Engn Aerosp Syst Design Lab Atlanta GA 30332 USA Rhein Westfal TH Aachen Inst Aeronaut & Astronaut D-52062 Aachen Germany

It is challenging to assess new technology in complex, interdisciplinary integrated systems, such as air transportation systems. Conflicting disciplines and technologies are always involved in aerospace systems design processes. Multicriteria Decision Analysis techniques can help decision makers to effectively deal with such situations and make wise design decisions. There is a variety of existing methods;thus, selection of the most appropriate method is critical because the use of inappropriate methods is often the cause of misleading design decisions. In this paper, an appropriateness index is used to quantify the goodness of a method for solving the problem under consideration. This method selection approach is implemented and an intelligent knowledge-based system is developed consisting of a multicriteria decision analysis library storing widely used decision analysis methods and a knowledge base providing the information required for the method selection process. Furthermore, a new approach for uncertainty assessment in the decision analysis process is proposed in this study. This novel approach for uncertainty assessment can be used to aggregate input data from tools with different fidelity levels and is capable of propagating uncertainties in an assessment chain. A business aircraft evaluation problem is conducted as a proof of implementation.

关键词： Decision Support System Business Aircraft Air Transportation System Artificial Intelligence Aerospace System Bombardier Challenger 300 Sensitivity Analysis binary search algorithm Probability Distribution Aircraft Conceptual Design

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Real-time Footstep Planning and Following for Navigation of Humanoid Robots

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JOURNAL OF ELECTRICAL ENGINEERING & TECHNOLOGY 2015年第5期10卷 2142-2148页

作者： Hong, Young-Dae Ajou Univ Dept Elect & Comp Engn Suwon 441749 South Korea

This paper proposes novel real-time footstep planning and following methods for the navigation of humanoid robots. A footstep command is defined by a walking direction and step lengths for footstep planning. The walking direction is determined by a uni-vector field navigation method, and the allowable yawing range caused by hardware limitation is considered. The lateral step length is determined to avoid collisions between the two legs while walking. The sagittal step length is modified by a binary search algorithm when collision occurs between the robot body and obstacles in a narrow space. If the robot body still collides with obstacles despite the modification of the sagittal step length, the lateral step length is shifted at the next footstep. For footstep following, a walking pattern generator based on a 3-D linear inverted pendulum model is utilized, which can generate modifiable walking patterns using the zero-moment point variation scheme. Therefore, it enables a humanoid robot to follow the footstep command planned for each footstep. The effectiveness of the proposed method is verified through simulation and experiment.

关键词： Humanoid robot Footstep planning Uni-vector field navigation method binary search algorithm Footstep following Modifiable walking pattern

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Variable-Horizon Guidance for Autonomous Rendezvous and Docking to a Tumbling Target

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JOURNAL OF GUIDANCE CONTROL AND DYNAMICS 2022年第5期45卷 846-858页

作者： Leomanni, Mirko Quartullo, Renato Bianchini, Gianni Garulli, Andrea Giannitrapani, Antonio Univ Siena Dept Informat Engn I-53100 Siena Italy Univ Siena Dept Informat Engn & Math I-53100 Siena Italy Univ Perugia I-06125 Perugia Italy

In this paper, the trajectory planning problem for autonomous rendezvous and docking between a controlled spacecraft and a tumbling target is addressed. The use of a variable planning horizon is proposed in order to construct an appropriate maneuver plan, within an optimization-based framework. The involved optimization problem is nonconvex and features nonlinear constraints. The main contribution is to show that such problem can be tackled effectively by solving a finite number of linear programs. To this aim, a specifically conceived horizon search algorithm is employed in combination with a polytopic constraint approximation technique. The resulting guidance scheme provides the ability to identify favorable docking configurations, by exploiting the time-varying nature of the optimization problem endpoint. Simulation results involving the capture of the nonoperational EnviSat spacecraft indicate that the method is able to generate optimal trajectories at a fraction of the computational cost incurred by a state-of-the-art nonlinear solver.

关键词： Autonomous Rendezvous and Docking Envisat binary search algorithm Convergence Analysis Model Predictive Control Trajectory Optimization Fuel Consumption Mixed Integer Linear Programming ESA Orbital Debris

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A Novel Circuit for Clock Synchronization Using binary search Scheme and Phase Interpolation

A Novel Circuit for Clock Synchronization Using Binary Searc...

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2015 IEEE 16th International Conference on Communication Technology(ICCT 2015)

作者： Chong Lu Zhi-kui Duan Yi Ding Yu Li Hong-zhou Tan SYSU-CMU Shunde International Joint Research Institute Sun Yat-sen University School of Information Science and Technology Sun Yat-sen University School of Computer Science and Technology Hunan University of Arts and Science

In this paper,a novel circuit for clock synchronization utilizing an interleaved delay line for coarse tuning and a phase interpolation component for fine tuning is *** interleaved delay line improves the precision to nearly half of conventional SMD and roughly aligns the output clock in two *** rest phase error is compensated by the fine tuning component with binary search scheme and phase interpolation in five clock cycles and the error is suppressed under *** circuit is designed and implemented using SMIC130 nm 1P8 M process with a 1.2 V voltage *** active area of proposed circuit is 260μm×140μm,and the total power consumption is 1.82mW@*** allowed operation frequency ranges from 200 MHz to860 MHz,and the duty cycle varies in[32%,77%].It is compatible with the clock distribution networks and clock tree synthesis workflow aided by EDA software.

关键词： Clock synchronizer Clock distribution network Interleaved delay line binary search algorithm Phase interpolation

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5 GHz all-digital delay-locked loop for future memory systems beyond double data rate 4 synchronous dynamic random access memory

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ELECTRONICS LETTERS 2015年第24期51卷 1973-1974页

作者： Lee, Dongyeol Kim, Jongsun Hongik Univ Elect & Elect Engn Seoul 121791 South Korea

A new low-power, fast-locking, all-digital delay-locked loop (DLL) that uses a disposable time-to-digital converter (TDC) is presented for future memory systems beyond double data rate 4. To achieve fast locking and high-frequency operation, the proposed DLL utilises a new hybrid (TDC + binary + sequential) search algorithm that results in a fast locking time of 11 clock cycles without the false lock and harmonic lock problems. By minimising the intrinsic delay of the digital delay line, the proposed DLL achieves an operating frequency range of 1.5-5.0 GHz which is higher than that of the current state-of-the-art all-digital DLLs. The DLL is fabricated in a 65 nm CMOS process and it achieves a peak-to-peak (p-p) output clock jitter of 14 ps (with a p-p input clock jitter of 8 ps) at 5 GHz. The DLL consumes 6.9 mW at 1 V and occupies an active area of 0.025 mm(2).

关键词： random-access storage time-digital conversion search problems clocks CMOS memory circuits timing jitter synchronisation low-power electronics memory systems synchronous dynamic random access memory all-digital delay-locked loop low-power DLL fast-locking DLL time-to-digital converter hybrid search algorithm TDC search algorithm binary search algorithm sequential search algorithm clock cycles harmonic lock problems intrinsic delay digital delay line CMOS process peak-to-peak output clock jitter p-p output clock jitter frequency 1 5 GHz to 5 0 GHz size 65 nm power 6 9 mW voltage 1 V size 0 025 mm

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A Linear Identification of Diode Models from Single I-V Characteristics of PV Panels

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS 2015年第7期62卷 4181-4193页

作者： Lim, Li Hong Idris Ye, Zhen Ye, Jiaying Yang, Dazhi Du, Hui Univ Glasgow Dept Elect Syst Glasgow G12 8QQ Lanark Scotland REC Cells Pte Ltd Singapore 637312 Singapore Natl Univ Singapore SERIS Singapore 117574 Singapore

This paper presents a novel approach on diode model parameter identification from the I-V characteristics of photovoltaic panels. Other than the prevailing methodology of solving a group of nonlinear equations from a few points on the I-V curve, the proposed methodology views the diode model as the equivalent output of a dynamic system. From this new viewpoint, diode model parameters are linked to the transfer function (after Laplace transform) of the same dynamic system whose parameters are then identified by a simple integral-based linear square. The indoor flash test shows the accuracy and effectiveness of the proposed method, and outdoor module testing shows its ability of online monitoring and diagnostics. Comparisons to the methods of Lambert W function and evolution algorithms are also included.

关键词： binary search algorithm diode model I-V characteristics linear least squares

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Simplified methods for the analysis of self-excited induction generators

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IET ELECTRIC POWER APPLICATIONS 2017年第9期11卷 1636-1644页

作者： Arthishri, Krishnan Anusha, Kumaresan Kumaresan, Natarajan Kumar, Subramaniam Senthil Natl Inst Technol Dept Elect & Elect Engn Tiruchirappalli Tamil Nadu India Govt Coll Engn Dept Elect & Elect Engn Tiruchirappalli Tamil Nadu India

In this study, two simple methods for the steady-state analysis of self-excited induction generators (SEIGs) are proposed. These methods neither require lengthy mathematical derivations nor any advanced optimisation techniques to solve the equivalent circuit of SEIGs. First method involves a simple linear search algorithm and the second method employs a binary search algorithm to find the operating frequency at any given rotor speed, leading to the performance predetermination of SEIGs. To start the search techniques, a systematic approach has been formulated for fixing the boundary values required for the unknown pu frequency. The efficacy of the proposed methods has been demonstrated by presenting the predetermined performance characteristics of a three-phase, 230V, four-pole, 50Hz SEIG. The same SEIG was also tested in the laboratory using a DC motor as the prime mover. The closeness observed between the predetermined values and the experimental results further confirms the validity of the search algorithms. It has also been shown that the proposed methods can be extended with the same simplicity, for carrying out the performance predetermination of the short-shunt configuration of SEIGs, used for obtaining improved voltage regulation with lagging power factor loads.

关键词： asynchronous generators power factor equivalent circuits rotors search problems DC motors voltage control lagging power factor loads improved voltage regulation short-shunt configuration prime mover DC motor three-phase four-pole SEIG predetermined performance characteristics boundary values rotor speed binary search algorithm linear search algorithm equivalent circuit steady-state analysis self-excited induction generators

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Computer-aided decision for human task allocation with mono- and multi-performance evaluation

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INTERNATIONAL JOURNAL OF PRODUCTION REsearch 2005年第21期43卷 4559-4588页

作者： Bennour, M Crestani, D Crespo, O Prunet, F Lab Informat Robot & Microelect Montpellier F-34392 Montpellier France

An efficient binary search-based approach used to determine the sets of human resources allowing one to reach, for an enterprise process, a given performance level is presented. It is based on an enterprise process performance methodology integrating human skill influence. In a first step, this approach is compared with algorithms such as Hybrid Taboo-Descent, Simulated Annealing and Knapsack algorithms for different performance points of view (temporal, financial, quality oriented) on limited and large complexity examples. In a second step, this approach is generalized to integrate simultaneously several viewpoints.

关键词： human resource allocation performance estimation binary search algorithm

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