作者：
Li, HaihuaLei, Ka-MengMartins, Rui P.Mak, Pui-InUniv Macau
Fac Sci & Technol Elect & Comp Engn ECE State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China Univ Macau
Fac Sci & Technol Elect & Comp Engn ECE State Key Lab Analog & Mixed Signal VLSI Macau Peoples R China
This article reports a 12-/13.56-MHz fast-and-energy-efficient startup crystal oscillator (XO) featuring a binary-search-assisted two-step injection technique for ultralow-power duty-cycled radios. Specifically, after...
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This article reports a 12-/13.56-MHz fast-and-energy-efficient startup crystal oscillator (XO) featuring a binary-search-assisted two-step injection technique for ultralow-power duty-cycled radios. Specifically, after the first injection, a calibration module refines the auxiliary oscillator's frequency toward the crystal's resonant frequency in a binary-search fashion with a sub-500-ppm error for the second injection. This calibration method eliminates the closed-loop phase-locked loop (PLL) and shortens the calibration period into 48 clock cycles. Prototyped in a 65-nm CMOS process, the XO occupies an active area of 0.134 mm(2). The 13.56-MHz XO can achieve a startup time (t(s)) of 45.8 mu s with a V-DD of 0.7 V, while consuming 5.0 nJ of energy. t(s) varies by +/- 2.2% amid temperature variations (-40 degrees C to 85 degrees C). Its steady-state power consumption is 28.4 mu W, with an output phase noise of -143.7 dBc/Hz at 1-kHz offset (FoM: 241.8 dBc/Hz), manifesting its state-of-the-art performance.
Quality of 3D point cloud maps is essential for navigation and localization in Autonomous Mobile Robots, yet creating these maps for large-scale areas presents challenges, stemming from the processing of numerous poin...
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Quality of 3D point cloud maps is essential for navigation and localization in Autonomous Mobile Robots, yet creating these maps for large-scale areas presents challenges, stemming from the processing of numerous points. In such situations, constructing a 3D map can be accomplished by dividing it into smaller regions and then merging them to generate a complete map by performing a 3D map stitching algorithm. Currently, these overlapping areas are manually selected, which leads to potential errors. In response, a novel method to automatically identify overlapping areas is proposed to perform map stitching based on the overlapping areas only instead of the entire maps. Utilizing the proposed method results in a significant reduction in time consumption. The proposed automatic method incorporates the DBSCAN algorithm for clustering, template matching for identifying corresponding clusters, and a binary-search algorithm for parameter optimization. The proposed method was evaluated on several large-scale 3D maps, including the KITTI dataset, and compared against manual selection and the use of entire maps in the map-merge-3D algorithm. The method achieves a significant reduction in the time required for the 3D map stitching process, amounting to a 38.64% decrease compared to using the entire maps. In terms of accuracy, the proposed method reduces translation error to 0.1723m and rotation error to 0.1763 degrees, representing decreases of 5.28% and 16.16%, respectively, while manual selection results in a translation error of 0.4278m and rotation error of 0.7123 degrees, increases of 135.25% and 238.75% respectively, compared to the entire maps 0.1819m and 0.2103 degrees.
Fast data search is an important element of big data in the modern era of internet of things, cloud computing, and social networks. search using traditional binary-search algorithm can be accelerated by employing an i...
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Fast data search is an important element of big data in the modern era of internet of things, cloud computing, and social networks. search using traditional binary-search algorithm can be accelerated by employing an interpolation search technique when the data is regularly distributed. In this work, the interpolation search is investigated in which the search results provided unexpected sluggish progress during a search in a large database due to the irregular distribution of data. Irregular distribution of data does not allow the interpolation to make a good prediction about the location of the search item. To overcome this issue, an interpolation-extrapolation search (IES) method is proposed where the interpolation method is integrated with an extrapolation method that balances the lower and upper bounds of the search interval. The proposed method provides faster convergence property than the binarysearch and the interpolation method. Hence, the proposed IES method provides a faster search for items in a big database.
This paper presents a single channel, low power 6-bit 410-MS/s asynchronous successive approximation register analog-to-digital converter （SAR ADC） for ultrawide bandwidth （UWB） communication, prototyped in a SMIC...
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This paper presents a single channel, low power 6-bit 410-MS/s asynchronous successive approximation register analog-to-digital converter （SAR ADC） for ultrawide bandwidth （UWB） communication, prototyped in a SMIC 65-nm process. Based on the 3 bits/stage structure, resistive DAC, and the modified asynchronous successive approximation register control logic, the proposed ADC attains a peak spurious-free dynamic range （SFDR） of 41.95 dB, and a signal-to-noise and distortion ratio （SNDR） of 28.52 dB for 370 MS/s. At the sampling rate of 410 MS/s, this design still performs well with a 40.71-dB SFDR and 30.02-dB SNDR. A four-input dynamic comparator is designed so as to decrease the power consumption. The measurement results indicate that this SAR ADC consumes 2.03 mW, corresponding to a figure of merit of 189.17 fJ/step at 410 MS/s.
This paper presents a single channel, low power 6-bit 410-MS/s asynchronous successive approximation register analog-to-digital converter (SAR ADC) for wireless sensor network (WSN) applications, prototyped in a 65nm ...
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ISBN:
(纸本)9781479948857
This paper presents a single channel, low power 6-bit 410-MS/s asynchronous successive approximation register analog-to-digital converter (SAR ADC) for wireless sensor network (WSN) applications, prototyped in a 65nm CMOS process. Through adopting the modified asynchronous binary-search successive approximation control logic and producing 3bits/stage, the proposed ADC achieves a peak spurious-free dynamic range (SFDR) of 41.95-dB, signal-to-noise and distortion ratio (SNDR) of 28.52-dB for 370 MS/s. At the sampling rate of 410 MS/s, this design still performs well with the 40.71-dB SFDR and 30.02-dB SNDR. A differential four-input dynamic comparator is designed so as to decrease the power consumption. The measurement results indicate that this SAR ADC consumes 2.03mW at a 1V power supply, corresponding to a figure of merit (FOM) of 189.17fJ/step.
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