检索结果-内蒙古大学图书馆

Minimized Area and High Speed EBCOT Architecture for JPEG 2000

Research Journal of Applied Sciences, Engineering and Technology 2017年第11期14卷 414-417页

作者： S. Vijayaraghavan C. Parthasarathy Department of ECE Department of IT SCSVMV University Kanchipuram India

In this study we have proposed minimized area and high speed EBCOT architecture for JPEG 2000. Embedded block coding with optimized truncation is an algorithm in JPEG 2000 image compression system. In several existing high speed EBCOT architecture is there in our proposed it overcomes and produce code generation. In our study open that image rate of more context dual generation is about 74.8%. To encoding the all image samples in a column, a new formulated named as pact context coding is invented as a important, high devised is used for less hardware. The proposed architecture is described in VHDL language, verified by simulation and successfully implemented in a Cyclone II and Stratix III FPGA. It provides a major reduction in memory access requirements, as well as a net increase of the processing speed as shown by the simulations. The C*D Quantizer coder is improved by the operating system and stage. The full design of processor encoder is tested on FPGA based. The results show that invented of the proposed architecture 172.28 M samples/sec is equaling to encode 1920*1080 (4:3:3) HD camera picture sequence at 39 f/sec. the bit plane architecture operates 315.06 MHZ which that implies that it is 4.03 times faster than the but plan coder so far. It is used many applications like satellite image, medical image and image compression system.

关键词： Architecture bit plane coder EBCOT FPGA JPEG 2000

来源：评论

学校读者我要写书评

暂无评论

A HIGH SPEED bit plane coder FOR JPEG 2000 AND IT'S FPGA IMPLEMENTATION

A HIGH SPEED BIT PLANE CODER FOR JPEG 2000 AND IT'S FPGA IMP...

引用

European signal processing conference

作者： Kishor Sarawadekar Swapna Banerjee Department of E & ECE I.I.T. Kharagpur

ISBN: (纸本)9781617388767

In this paper an optimized architecture of bit plane coder for Embedded Block Coding with Optimal Truncation (EBCOT) algorithm targeting its FPGA implementation is proposed. Although several speed up techniques exist, we present architecture whose performance is improved based on detailed analysis of data path used to obtain context windows. Multiplexer based coding style is adapted to utilize the resources optimally. The proposed design works at 67 MHz after post placement and routing on Xilinx XC2V1000 device. Even though 18 bit planes are used, the implementation results show that the consumption of logic resources in terms of LUTs, slices and flip-flop slices have reduced drastically compared to that of reported designs [1, 2, 3, 4, 5 and 6]. Moreover, power consumption is also moderate.

关键词： JPEG2000 EBCOT bit plane coder JPEG ENcoder channels (data transmission) High speed Building construction ARCHITECTURE Network routing MULTIPLEXOR

来源：评论

学校读者我要写书评

暂无评论

High Speed and Bi-mode Image Compression Core for Onboard Space Application

High Speed and Bi-mode Image Compression Core for Onboard Sp...

引用

International Conference on Space Information Technology 2009

作者： Wang, Huaichao Chen, Jun Gu, Xiaodong Chen, Xiaomin Chinese Acad Sci Ctr Space Sci & Appl Res Beijing 100190 Peoples R China

ISBN: (纸本)9780819480798

This paper presents a bi-mode, high performance Discrete Wavelet Transform-based image compression core for future spacecrafts and micro-satellites. The hardware solution proposed here exploits an optimized CCSDS IDC algorithm and consists of a lossless mode and a lossly mode. The throughput of the core is improved 40 times using parallel architecture and pipeline technique, and a data rate of about 12.5M pixles/s can be sustained at 50MHz for the lossly mode. The experimental results indicate that this core has high performance at coding efficiency, data rate and error containment for both of the two modes.

关键词： CCSDS image compression bi-mode DWT optimized architecture bit plane coder

来源：评论

学校读者我要写书评

暂无评论

Design and Implementation of Image Compression Core Based on CCSDS Algorithm

Design and Implementation of Image Compression Core Based on...

引用

4th International Conference on Computer Science and Education

作者： Gu Xiaodong Wang Huaichao Zhang Xuequan Xu Shijun Chinese Acad Sci Ctr Space Sci & Appl Res Beijing Peoples R China Xian Technol Univ Dept Math & Phys Xian Peoples R China

ISBN: (纸本)9781424435197

Image compression is one of the major services in space flight mission and remote sensing system. This paper presents a high speed and high performance image compressor for future spacecrafts and micro-satellites. The proposed compression core is based on a modified CCSDS algorithm and the processing speed is improved 40 times using parallel architecture and pipeline technique. The experimental results indicate that this core has high performance at coding efficiency, data rate and error containment. A data rate of about 12.5Mpixels/s can be sustained at 50MHz.

关键词： CCSDS image compression DWT parallel processing pipeline bit plane coder

来源：评论

学校读者我要写书评

暂无评论

EFFICIENT VLSI ARCHITECTURE FOR bit plane ENcoder OF JPEG 2000

EFFICIENT VLSI ARCHITECTURE FOR BIT PLANE ENCODER OF JPEG 20...

引用

16th IEEE International Conference on Image Processing

作者： Sarawadekar, Kishor Banerjee, Swapna Indian Inst Technol Kharagpur Dept E & ECE Kharagpur W Bengal India

ISBN: (纸本)9781424456536

In this paper an optimized architecture of bit plane coder for Embedded Block Coding with Optimal Truncation (EBCOT) algorithm targeting its FPGA implementation is proposed. Although several speed up techniques exist, we present architecture whose performance is improved based on detailed analysis of data path used to obtain context windows. Multiplexer based coding style is adapted to utilize the resources optimally. After place and route on Xilinx XC2VP30 the proposed design operates at 82 MHz which is capable of encoding 720p (HDTV 1280 x 720, 4:2:2) pictures at nearly 44 frames per second. Even though 14 bit planes are used, the implementation results show that the consumption of logic resources in terms of LUTs, slices and flip-flop slices have reduced drastically compared to that of reported designs [1, 2, 3, 4 and 5].

关键词： JPEG 2000 EBCOT bit plane coder

来源：评论

学校读者我要写书评

暂无评论

Concurrent symbol processing capable VLSI architecture for bit plane coder of JPEG2000

引用

IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS 2005年第8期E88D卷 1878-1884页

作者： Gupta, AK Nooshabadi, S Taubman, D UNSW Fac Elect Engn Sydney NSW Australia

JPEG2000 image compression standard is designed to cater the needs of a large span of applications including numerous consumer products. However, its use is restricted due to the high hardware cost involved in its implementation. bit plane coder (BPC) is the main resource intensive component of JPEG2000. Its throughput plays a key role in deciding the overall throughput of a JPEG2000 encoder. In this paper we present the algorithm and parallel pipelined VLSI architecture for BPC which processes a complete stripe-column concurrently during every pass. The hardware requirements and the critical path delay of the proposed technique are compared with the existing solutions. The experimental results show that the proposed architecture has 2.6 times greater throughput than existing architectures, with a comparatively small increase in hardware cost.

关键词： JPEG2000 concurrent symbol processing bit plane coder VLSI architecture

来源：评论

学校读者我要写书评

暂无评论

Novel efficient architecture for JPEG2000 entropy coder

Novel efficient architecture for JPEG2000 entropy coder

引用

Conference on Visual Communications and Image Processing 2003

作者： Fatemi, O Asadzadeh, P Univ Teheran Dept Elect & Comp Engn Tehran Iran

ISBN: (纸本)0819450235

With the continual expansion of multimedia and Internet applications, the needs and requirements of advanced technologies, grew and evolved. With the increasing use of multimedia technologies, image compression techniques require higher performance as well as new features. Significant progress has recently been made in image compression techniques using discrete wavelet transforms. The overall performance of these schemes may be further improved by properly designing of efficient entropy coders. In this paper, we describe an efficient architecture for JPEG2000 entropy coder, which is a new standard to address the needs in the specific area of still image encoding. Our proposed architecture consists of two main parts, the coefficient bit modeler (CBM) and the binary arithmetic coder (BAC), which communicate through a FIFO buffer. Optimizations have been made in our proposed architecture to reduce accesses to memories. Our Proposed architecture is fast and modular and is suitable for real-time applications.

关键词： JPEG2000 context-based arithmetic coding coefficient bit modeler CBM bit plane coder BPC binary arithmetic coder BAC

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：