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Soft-input bit-flipping decoding of generalised concatenated codes for application in non-volatile flash memories

IET COMMUNICATIONS 2019年第4期13卷 460-467页

作者： Rajab, Mohammed Shavgulidze, Sergo Freudenberger, Juergen Univ Appl Sci HTWG Konstanz ISD Constance Germany Georgian Tech Univ Fac Power Engn & Telecommun Tbilisi Georgia

Error correction coding based on soft-input decoding can significantly improve the reliability of non-volatile flash memories. This work proposes a soft-input decoder for generalised concatenated (GC) codes. GC codes are well suited for error correction in flash memories for high reliability data storage. The authors propose GC codes constructed from inner extended binary Bose-Chaudhuri-Hocquenghem (BCH) codes and outer Reed-Solomon (RS) codes. The extended BCH codes enable an efficient hard-input decoding. Furthermore, a low-complexity soft-input decoding method is proposed. This bit-flipping decoder uses a fixed number of test patterns and an algebraic decoder for soft-decoding. An acceptance criterion for the final candidate codeword is proposed. Combined with error and erasure decoding of the outer RS codes, this acceptance criterion can improve the decoding performance and reduce the decoding complexity. The presented simulation results show that the proposed bit-flipping decoder in combination with outer error and erasure decoding can outperform maximum-likelihood decoding of the inner codes.

关键词： extended BCH codes erasure decoding parity check codes candidate codeword low-complexity soft-input decoding method Reed-Solomon codes outer Reed–Solomon codes Memory circuits inner extended binary Bose–Chaudhuri–Hocquenghem codes Codes outer RS codes decoding complexity algebraic decoder soft-input bit-flipping decoding test patterns decoding soft-input decoder binary codes decoding performance BCH codes error correction coding high reliability data storage error correction codes flash memories acceptance criterion maximum-likelihood decoding efficient hard-input decoding nonvolatile flash memories GC codes concatenated codes random-access storage bit-flipping decoder integrated circuit reliability generalised concatenated codes

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Reduced complexity hard- and soft-input BCH decoding with applications in concatenated codes

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IET CIRCUITS DEVICES & SYSTEMS 2021年第3期15卷 284-296页

作者： Freudenberger, Juergen Bailon, Daniel Nicolas Safieh, Malek Univ Appl Sci Inst Syst Dynam ISD HTWG Konstanz Constance Germany

Error correction coding for optical communication and storage requires high rate codes that enable high data throughput and low residual errors. Recently, different concatenated coding schemes were proposed that are based on binary BCH codes with low error correcting capabilities. In this work, low-complexity hard- and soft-input decoding methods for such codes are investigated. We propose three concepts to reduce the complexity of the decoder. For the algebraic decoding we demonstrate that Peterson's algorithm can be more efficient than the Berlekamp-Massey algorithm for single, double, and triple error correcting BCH codes. We propose an inversion-less version of Peterson's algorithm and a corresponding decoding architecture. Furthermore, we propose a decoding approach that combines algebraic hard-input decoding with soft-input bit-flipping decoding. An acceptance criterion is utilised to determine the reliability of the estimated codewords. For many received codewords the stopping criterion indicates that the hard-decoding result is sufficiently reliable, and the costly soft-input decoding can be omitted. To reduce the memory size for the soft-values, we propose a bit-flipping decoder that stores only the positions and soft values of a small number of code symbols. This method significantly reduces the memory requirements and has little adverse effect on the decoding performance.

关键词： decoding approach Berlekamp-Massey algorithm error correction coding triple error correcting BCH codes soft-input BCH decoding optical communication low error correcting capabilities double error correcting BCH codes error correction BCH codes decoding concatenated coding schemes soft-values bit-flipping decoder binary codes Peterson's algorithm high data throughput low-complexity hard-input decoding methods error correction codes single error correcting BCH codes low residual errors concatenated codes soft values reduced complexity hard-input BCH decoding soft-input bit-flipping decoding low-complexity soft-input decoding methods code symbols algebraic hard-input decoding high rate codes binary BCH codes decoding architecture decoding performance soft-input decoding parity check codes algebraic decoding

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Network coding schemes with efficient LDPC coded MIMO-NOMA in two-way relay networks

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IET COMMUNICATIONS 2020年第2期14卷 337-348页

作者： Hlaing, Ngu War Farzamnia, Ali Mariappan, Muralindran Haldar, Manas Kumar Univ Malaysia Sabah Fac Engn Kota Kinabalu Sabah Malaysia

The combination of non-orthogonal multiple access (NOMA) and multi-input multi-output (MIMO) approaches has been considered as assuring multiple access for the fifth generation technology. In this study, the performance of a $2\times 2$2x2 MIMO-NOMA system with low-density parity check (LDPC) codes is investigated. Redundancy with randomly interleaved differential encoding (R-RIDE) is proposed and applied to LDPC encoded messages by two users. LDPC decoding is done using the sum-product algorithm (SPA), which has two types of decoding methods, hard-decision and soft-decision. For hard-decision, bit-flipping decoder is used and for soft-decision, probability domain, log-domain, and simplified log-domain decoders are used. bit error rate (BER) versus signal-to-noise ratio (SNR) in (dB) and average mutual information (AMI) in (bps/Hz) versus SNR (dB) are evaluated to compare the performance of the proposed and conventional LDPC schemes in NOMA and MIMO-NOMA systems. Simulation results show that both AMI and BER of the proposed LDPC-R-RIDE in MIMO-NOMA system greatly outperforms conventional LDPC coded schemes in NOMA and MIMO-NOMA systems. Moreover, the proposed R-RIDE-LDPC in MIMO-NOMA system outperforms the proposed scheme in the NOMA system. From the simulation results, LDPC-R-RIDE with simplified log-domain decoder has the best AMI result and BER performance compared with other decoding methods.

关键词： encoding error statistics decoding MIMO communication parity check codes network coding schemes efficient LDPC nonorthogonal multiple access multiinput multioutput approaches $2\times 2$2x2 MIMO-NOMA low-density parity check codes LDPC encoded messages exclusive-OR coded information LDPC decoding decoding methods hard-decision decoding soft-decision decoding bit-flipping decoder simplified log-domain decoders R-RIDE-LDPC conventional LDPC MIMO-NOMA system LDPC-R-RIDE simplified log-domain decoding

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Security and complexity of the McEliece cryptosystem based on quasi-cyclic low-density parity-check codes

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IET INFORMATION SECURITY 2013年第3期7卷 212-220页

作者： Baldi, Marco Bianchi, Marco Chiaraluce, Franco Univ Politecn Marche Dipartimento Ingn Informaz Ancona Italy

In the context of public key cryptography, the McEliece cryptosystem represents a very smart solution based on the hardness of the decoding problem, which is believed to be able to resist the advent of quantum computers. Despite this, the original McEliece cryptosystem based on Goppa codes, has encountered limited interest in practical applications, partly because of some constraints imposed by this very special class of codes. The authors have recently introduced a variant of the McEliece cryptosystem including low-density parity-check codes, that are state-of-the-art codes, now used in many telecommunication standards and applications. In this study, the authors discuss the possible use of a bit-flipping decoder in this context, which gives a significant advantage in terms of complexity. The authors also provide theoretical arguments and practical tools for estimating the trade-off between security and complexity, in such a way to give a simple procedure for the system design.

关键词： cyclic codes decoding Goppa codes parity check codes public key cryptography McEliece cryptosystem complexity quasicyclic low-density parity-check codes public key cryptography decoding problem quantum computers Goppa codes telecommunication standards bit-flipping decoder system design

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Hardware Optimization of the Perturbation for Probabilistic Gradient Descent bit flipping decoders 50

Hardware Optimization of the Perturbation for Probabilistic ...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Le, Khoa Ghaffari, Fakhreddine Declercq, David Vasic, Bane ENSEA UCP CNRS ETIS UMR 8051 Cergy Pontoise France Univ Arizona Dept Elect & Comp Engn Tucson AZ 85719 USA

ISBN: (纸本)9781467368537

The Probabilistic Gradient Descent bit-flipping (PGDBF) decoder has been proposed as a very promising hard-decision Low-Density Parity-Check (LDPC) decoder with a large gain in error correction. However, this impressive decoding gain is reported to come along with a non-negligible extra complexity due to the additional Perturbation Block (PB) required on top of the Gradient Descent bit-flipping (GDBF) decoder. In this paper, an efficient solution to implement this PB is introduced which is shown to keep the decoding gain as good as the theoretical PGDBF decoder while requiring a very small hardware overhead compared to the non-probabilistic GDBF. The proposed architecture is designed basing on a statistical analysis conducted to find the key features of the randomness needed to maintain the decoding gain and to reveal the simplification directions. The efficiency of our proposed method is confirmed by the synthesis results of decoder implementations on ASIC with 65nm CMOS technology and performance simulations.

关键词： Low-Density Parity-Check bit-flipping decoder random generator low-complexity implementation

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Efficient BIKE Hardware Design with Constant-Time decoder

Efficient BIKE Hardware Design with Constant-Time Decoder

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IEEE International Conference on Quantum Computing and Engineering (QCE)

作者： Reinders, Andrew H. Misoczki, Rafael Ghosh, Santosh Sastry, Manoj R. Intel Corp Intel Labs Secur & Privacy Res 2111 NE 25th Ave Hillsboro OR 97124 USA

ISBN: (纸本)9781728189697

BIKE (bit-flipping Key Encapsulation) is a promising candidate under consideration in the NIST Post-Quantum Cryptography Standardization process. It is a code-based cryptosystem with a simple definition and well-understood underlying security. The most critical step in this cryptosystem consists of correcting errors with a QC-MDPC linear code. Published performance on 64-bit processors shows this decode procedure takes 20M cycles for the software implementation, and worse for embedded devices. In this paper, we propose a BIKE coprocessor that accelerates the operations least suitable to embedded software implementation, enabling power-constrained SoC devices to directly implement BIKE with good performance. We propose a simplification of the grey-black decoder in the BIKE spec, which is more friendly to hardware implementations, and demonstrate the performance of this decoder on an Intel Arria 10 FPGA platform. Our implementation has a cycle-area performance comparable to other MDPC decoders in the literature, while including design elements which may facilitate power side channel resilience. The main result is to enable BIKE to be run on small SoC platforms, and therefore for those devices to resist attacks by quantum computers.

关键词： Post-Quantum Cryptography (PQC) BIKE QC-MDPC bit-flipping decoder Hardware Implementation NIST PQC Standardization Project

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Low-complexity LDPC decoder for Physical Layer Network Coded Multi-way Wireless Relay Systems 10

Low-complexity LDPC Decoder for Physical Layer Network Coded...

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10th IEEE International Conference on Industrial and Information Systems (ICIIS)

作者： Balasuriya, Nuwan Wavegedara, Chandika B. Univ Moratuwa Dept Elect & Telecommun Engn Moratuwa Sri Lanka

ISBN: (纸本)9781479918768

Recently, in multi-way relay systems employing physical-layer network coding (PNC), channel condition-based pair selection for pairwise information exchange has drawn increased attention as it provides improved performance over the alternative approaches such as round-robin scheduling of node pairs. With pairwise information exchange, there is additional time diversity available due to transmission of the same coded information block of most of the nodes twice in two adjacent time slots. This additional time diversity can be exploited to further enhance the system performance by means of joint channel decoding-network coding. To this end, a joint belief propagation (BP)-based channel decoding-network coding algorithm was proposed by us in [9] for the relay node of low density parity check (LDPC)-coded multi-way relay systems. Even though the algorithm of [9] offers much superior performance over separate channel decoding, it is highly computational expensive and may not be suitable for applications in wireless sensor networks. Alternatively, bit-flipping (BF)-based LDPC decoding can be adopted at much lower computational complexity. In this paper, we develop a low complexity joint bit-flipping (BF) based channel decoding and network coding algorithm for LDPCbased multi-way relay systems. The BER performance of the proposed algorithm is investigated using computer simulation for two commonly used LDPC codes. The simulation results demonstrate that superior BER performance can be achieved using the proposed joint decoding algorithm over separate and independent bit-flipping-based LDPC channel decoding at the relay. The simulation results also verify that our proposed algorithm is capable of harnessing the aforesaid additional time diversity available. Though the performance of the proposed joint decoding algorithm is inferior to the BP-based algorithm of [9], due to its low computationally complexity, this algorithm may be appealing for applications in relay nodes wit

关键词： Multi-way relay channel physical layer network coding low density parity check codes (LDPC) bit-flipping decoder

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Performance Bounds for QC-MDPC Codes decoders 1

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9th International Workshop on Code-Based Cryptography (CBCrypto)

作者： Baldi, Marco Barenghi, Alessandro Chiaraluce, Franco Pelosi, Gerardo Santini, Paolo Univ Politecn Marche Ancona Italy Politecn Milan Milan Italy

ISBN: (数字)9783030983659

ISBN: (纸本)9783030983659;9783030983642

Quasi-Cyclic Moderate-Density Parity-Check (QC-MDPC) codes are receiving increasing attention for their advantages in the context of post-quantum asymmetric cryptography based on codes. However, a fundamentally open question concerns modeling the performance of their decoders in the region of a low decoding failure rate (DFR). We provide two approaches for bounding the performance of these decoders, and study their asymptotic behavior. We first consider the well-known Maximum Likelihood (ML) decoder, which achieves optimal performance and thus provides a lower bound on the performance of any sub-optimal decoder. We provide lower and upper bounds on the performance of ML decoding of QC-MDPC codes and show that the DFR of the ML decoder decays polynomially in the QC-MDPC code length when all other parameters are fixed. Secondly, we analyze some hard to decode error patterns for bit-flipping (BF) decoding algorithms, from which we derive some lower bounds on the DFR of BF decoders applied to QC-MDPC codes.

关键词： QC-MDPC codes Decoding failure rate bit-flipping decoder Maximum likelihood decoder Error floor Post-quantum cryptography Code-based cryptography

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