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International Conference on Advances in Electrical, Electronic and Systems Engineering (ICAEES)

作者： Pathan, Aneela Memon, Tayab D. Keerio, Sharmeen Kalwar, Imtiaz Hussain Mehran Univ Engn & Technol Inst Informat & Commun Technol Jamshoro Pakistan Quaid E Awam Univ Coll Engn Sci & Tecnol QUCEST Dept Elect Engn Larkana Pakistan Mehran Univ Engn & Technol Dept Elect Engn Jamshoro Pakistan

ISBN: (纸本)9781509028894

In this work, comparative analysis of booth and Wallace Tree multiplier architectures is presented using Altera small commercial FPGA devices. Comparison is done with respect to resources consumed and maximum frequency achieved for different multiplier bit width. The synthesis results show tradeoff that booth multiplier offers better performance at the cost of more chip area. This is very useful to guide in choosing suitable VLSI architecture as per required application.

关键词： booth algorithm Wallace Tree Multiplier Policies FPGA

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Efficient algorithm and Fast Hardware Implementation for Multiply-by-(1+2^k)

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IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 2015年第4期E98A卷 966-974页

作者： Wey, Chin-Long Jui, Ping-Chang Shiue, Muh-Tian Natl Chiao Tung Univ Dept Elect & Comp Engn Hsinchu Taiwan Natl Cent Univ Dept Elect Engn Taoyuan Taiwan

A constant multiplier performs a multiplication of a data-input with a constant value. Constant multipliers are essential components in various types of arithmetic circuits, such as filters in digital signal processor (DSP) units, and they are prevalent in modern VLSI designs. This study presents an efficient algorithm and fast hardware implementation for performing multiply-by-(1+2(k)) operation with additions. No multiplications are needed. The value of (1+2(k))N can be computed by adding N to its k-bit left-shifted value 2(k)N. The additions can be performed by the full-adder-based (FA-based) ripple carry adder (RCA) for simple architecture. This paper introduces the unit cells for additions (UCAs) to construct the UCA-based RCA which achieves 35% faster than the FA-based RCA in speed performance. Further, in order to improve the speed performance, a simple and modular hybrid adder is presented with the proposed UCA concept, where the carry lookahead adder (CLA) as a module and many of the CLA modules are serially connected in a fashion similar to the RCA. Results show that the hybrid adder significantly improves the speed performance.

关键词： constant multiplier ripple carry adder (RCA) carry-lookahead adder (CLA) hybrid adder (HyA) booth algorithm

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FPGA Implementation of Conventional and Vedic algorithm for Energy Efficient Multiplier

FPGA Implementation of Conventional and Vedic Algorithm for ...

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IEEE International Conference on Energy Systems and Applications (ICESA)

作者： Patil, Hemangi P. Sawant, S. D. NBN Singhgad Sch Engn E&TC Dept Pune Maharashtra India

ISBN: (纸本)9781467368179

Digital Signal Processor (DSP) as well as other microcontroller applications requires fast and low power consumption systems to compete with the advanced technology. The performance of the DSP applications mainly depends on the multiplier, because the multiplication requires more iterations, long time and large area of the system than other computations. Hence to improve the performance of the system it is required to have high speed and low power consumption multiplier. In this paper we proposed the comparative study of two different algorithms, first one is the conventional method called as "booth Multiplier" and other is the vedic method "Nikhilam Navatascaram Dasatah" using reversible logic gates. Both the multipliers are designed and implemented by using Xilinx 13.2 ISE simulator. Comparative results of both the multipliers are analyzed in terms of delay, area and power consumption.

关键词： booth algorithm computation delay Nikhilam algorithm power consumption reversible logic gates vedic mathematics

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Design and Implementation of Energy Efficient Vedic Multiplier using FPGA

Design and Implementation of Energy Efficient Vedic Multipli...

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IEEE International Conference on Information Processing (ICIP)

作者： Patil, Hemangi P. Sawant, S. D. NBN Singhgad Sch Engn E&TC Dept Pune Maharashtra India

ISBN: (纸本)9781467377584

The performance of the DSP applications mainly depends on the multiplier, because the multiplication requires more iterations, long time and large area of the system than other computations. Hence to improve the performance of the system it is required to have high speed and low power consumption multiplier. In this paper we proposed the comparative study of two different algorithms, first one is the conventional method called as "booth Multiplier" and other is the vedic method "Nikhilam Navatascaram Dasatah" using reversible logic gates. Both the multipliers are designed and implemented by using Xilinx 13.2 ISE simulator. Comparative results of both the multipliers are analyzed in terms of delay, area and power consumption.

关键词： booth algorithm Computation Delay Nikhilam algorithm Power Consumption Reversible Logic Gates Vedic Mathematics

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Performance Improvement of QPSK MODEM Implemented in FPGA.

Performance Improvement of QPSK MODEM Implemented in FPGA.

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International Conference on Smart Sensors and Systems (IC-SSS)

作者： Umesharaddy Sujatha, B. K. MS Ramaiah Inst Technol Dept Telecommun Engn Bangalore 54 Karnataka India

ISBN: (纸本)9781467393287

This paper proposes a Quadrature Phase Shift Keying (QPSK) using two different methods. QPSK is one of the forms of Phase Shift Keying (PSK) modulation scheme. Generally a conventional QPSK modulator with Direct Digital Synthesizer (DDS) and arithmetic multiplier separates base band signal into I and Q phase which consumes low throughput with complexity in hardware implementation. Hence to generate high throughput QPSK modulator, the first proposal uses an up and down accumulator for carrier generator instead of DDS and arithmetic multiplier is modified as booth multiplier. The second proposed method will produce the QPSK signal, which is based on stored QPSK phase data in ROM, which eliminates completely the DDS and multiplier blocks of the modulator.

关键词： QPSK Modulation booth algorithm Verilog FPGA

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Radix-4 and Radix-8 booth Encoded Multi-Modulus Multipliers

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2013年第11期60卷 2940-2952页

作者： Muralidharan, Ramya Chang, Chip-Hong Nanyang Technol Univ Sch Elect & Elect Engn Singapore 639798 Singapore

Novel multi-modulus designs capable of performing the desired modulo operation for more than one modulus in Residue Number System (RNS) are explored in this paper to lower the hardware overhead of residue multiplication. Two multi-modulus multipliers that reuse the hardware resources amongst the modulo 2(n) - 1, modulo 2(n) and modulo 2(n) + 1 multipliers by virtue of their analogous number theoretic properties are proposed. The former employs the radix-2(2) booth encoding algorithm and the latter employs the radix-2(3) booth encoding algorithm. In the proposed radix-2(2) and radix-2(3) booth encoded multi-modulus multipliers, the modulo-reduced products for the moduli, 2(n) - 1, 2(n) and 2(n) + 1 are computed successively. With the basis of the radix-2(2) booth encoded modulo 2(n) + 1 and radix-2(3) booth encoded modulo 2(n) - 1 and modulo 2(n) + 1 multiplier architectures, new booth encoded modulo multipliers are proposed to maximally share the hardware resources in the multi-modulus architectures. Our experimental results on {2(n) - 1, 2(n) - 1, 2(n) + 1} based RNS multiplication show that the proposed radix-2(2) and radix-2(3) booth encoded multi-modulus multipliers save nearly 60% of area over the corresponding single-modulus multipliers. The proposed radix-2(2) and radix-2(3) booth encoded multi-modulus multipliers increase the delay of the corresponding single-modulus multipliers by 18% and 13%, respectively in the worst case. Compared to the single-modulus multipliers, the proposed multi-modulus multipliers incur a minor power dissipation penalty of 5%.

关键词： booth algorithm multi-modulus architectures multiplier residue number system (RNS)

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Area-Power Efficient Modulo 2ⁿ-1 and Modulo 2ⁿ+1 Multipliers for {2ⁿ-1, 2ⁿ, 2ⁿ+1} Based RNS

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2012年第10期59卷 2263-2274页

作者： Muralidharan, Ramya Chang, Chip-Hong Nanyang Technol Univ Sch Elect & Elect Engn Singapore 639798 Singapore

Residue Number System (RNS) is often adopted to implement long and repetitive multiplications of cryptographic and signal processing algorithms. To sustain the competitive advantages of RNS over two's complement system in pervasive computing platforms, the hardware cost of parallel modulo arithmetic operations must be lowered. In this paper, new low power and low area modulo multipliers for the well-established {2(n) - 1, 2(n), 2(n) +1} based RNS are proposed. The proposed modulo 2(n) - 1 and 2(n) + 1 modulo multipliers are based on the radix-8 booth encoding technique. The requisite hard multiples in the critical path are generated by fast customized parallel-prefix adders. In the proposed modulo 2(n) - 1 multiplier, the number of partial products is lowered to left perpendicularn/3right perpendicular + 1, which is around 33% reduction over radix-4 booth encoded multiplier for n =32 - 64. For modulo 2(n) + 1 multiplication, the aggregate bias due to the hard multiple and the modulo-reduced partial product generations is composed of multiplier-dependent dynamic bias and multiplier-independent static bias. Both biases have been reduced by properties of modulo a2(n) + 1 arithmetic and merged into only three n-bit words. Consequently, the total number of partial products in the proposed modulo 2(n) + 1 multiplier is given by left perpendicularn/3right perpendicular + 6, which is 11% and 35% reduction over radix-4 booth encoded multiplier for n = 32 and 64, respectively. From synthesis results for {2(n) - 1, 2(n), 2(n) +1} based RNS multipliers constructed from different modulo 2(n-)+ 1 and modulo 2(n) + 1 multipliers, our proposed modulo multipliers save 4%-40% and 24%-34% area as well as 21%-40% and 7%-19% total power dissipation over radix-4 booth encoded and non-encoded modulo multipliers, respectively. These results are well correlated with the theoretical estimation based on the normalized area model.

关键词： booth algorithm computer arithmetic multiplication residue number system (RNS)

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A Digital Regulator for FPGA Implementation

A Digital Regulator for FPGA Implementation

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International Conference on Materials Science and Information Technology (MSIT 2011)

作者： Qian, Xiang-ping Qiao, Wei-ming Zhou, Zhong-zu Chen, Xi-meng Jing, Lan Chinese Acad Sci Inst Modern Phys Lanzhou Gansu Peoples R China Lanzhou Univ Sch Nucl Sci & Technol Lanzhou Gansu Peoples R China

ISBN: (纸本)9783037853191

A digital regulator architecture implemented in FPGA is described which is used in the accelerator power supply. To save the delay time, the device is based on combinational circuit and special data format. The multiplier uses the partial products generated by modified booth algorithm, Carry look-ahead adder and Wallace tree. The regulator is written in Verilog, and is synthesized into FPGA. The synthesis results shows that the proposed regulator can run 200MHZ clock rate in FPGA EP3C25F256 and the whole feedback time is as short as 3 clock periods.

关键词： digital regulator carry look-ahead adder booth algorithm Wallace tree

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Radix-8 booth Encoded Modulo 2ⁿ-1 Multipliers With Adaptive Delay for High Dynamic Range Residue Number System

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2011年第5期58卷 982-993页

作者： Muralidharan, Ramya Chang, Chip-Hong Nanyang Technol Univ Sch Elect & Elect Engn Singapore 639798 Singapore

A special moduli set Residue Number System (RNS) of high dynamic range (DR) can speed up the execution of very-large word-length repetitive multiplications found in applications like public key cryptography. The modulo 2(n) - 1 multiplier is usually the noncritical datapath among all modulo multipliers in such high-DR RNS multiplier. This timing slack can be exploited to reduce the system area and power consumption without compromising the system performance. With this precept, a family of radix-8 booth encoded modulo 2(n) - 1 multipliers, with delay adaptable to the RNS multiplier delay, is proposed. The modulo 2(n) - 1 multiplier delay is made scalable by controlling the word-length of the ripple carry adder, k employed for radix-8 hard multiple generation. Formal criteria for the selection of the adder word-length are established by analyzing the effect of varying k on the timing of multiplier components. It is proven that for a given n, there exist a number of feasible values of k such that the total bias incurred from the partially-redundant partial products can be counteracted by only a single constant binary string. This compensation constant for different valid combinations of n and k can be precomputed at design time using number theoretic properties of modulo 2(n) - 1 arithmetic and hardwired as a partial product to be accumulated in the carry save adder tree. The adaptive delay of the proposed family of multipliers is corroborated by CMOS implementations. In an RNS multiplier, when the critical modulo multiplier delay is significantly greater than the noncritical modulo 2(n) - 1 multiplier delay, k = n and k = n/3 are recommended for n not divisible by three and divisible by three, respectively. Conversely, when this difference diminishes, k is better selected as n/4 and n/6 for n not divisible by three and divisible by three, respectively. Our synthesis results show that the proposed radix-8 booth encoded modulo 2(n) - 1 multiplier saves substantial area

关键词： booth algorithm design space exploration modulo arithmetic multiplier residue number system (RNS)

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A Simple High-Speed Multiplier Design

A Simple High-Speed Multiplier Design

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12th World Multi-Conference on Systemics, Cybernetics and Informatics/14th International Conference on Information Systems Analysis and Synthesis

作者： Dowoud, D. S. Dawoud, Peter D. Charles, Ndagije Univ Kwazulu Natal Durban South Africa Natl Univ Rwanda Butare Rwanda

ISBN: (纸本)9781934272312

The performance of multiplication is crucial for multimedia applications such as 3D graphics and signal processing systems, which depend on the execution of large numbers of multiplications. Many algorithms are proposed to implement high speed parallel multipliers. These algorithms mainly focused on rapidly reducing the partial products rows down to final sums and carries used for the final accumulation. These techniques mostly rely on circuit optimization and minimization of the critical paths, This paper focuses on reducing the number of generated partial product rows before applying any of the partial products reduction techniques. Fewer partial products rows means lowering the overall operation time. The paper introduces two techniques for reducing the number of generated partial product rows. The first technique uses an algorithm and a circuit that result in finding the 2's complement in a fast way. The second technique uses the conventional way of getting the 2's complement (complement a binary number and add I to the complemented number), but a simple hardware is proposed to implement the "add 1" operation without any carry propagation. In addition to the speed improvement, our algorithms result in a true diamond-shape for the partial product tree, which is more efficient in terms of implementation. The simulation of our proposed techniques showed large improvement in speed and in power consumption when compared to conventional multiplication algorithms.

关键词： Multiplier booth algorithm modified booth encoding (MBE) partial products

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