This paper presents the implementation of a fault detection and correction technique used to design a robust 8051 micro-controller with respect to a particular transient fault called Single Event Upset (SEU). A specif...
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This paper presents the implementation of a fault detection and correction technique used to design a robust 8051 micro-controller with respect to a particular transient fault called Single Event Upset (SEU). A specific study regarding the effects of a SEU in the micro-controller behavior was performed. Furthermore, a fault tolerant technique was implemented in a version of the 8051. The VHDL description of the fault-tolerant microprocessor was prototyped in a FPGA environment and results in terms of area overhead, level of protection and performance penalties are discussed.
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