咨询与建议

限定检索结果

文献类型

  • 1 篇 会议

馆藏范围

  • 1 篇 电子文献
  • 0 种 纸本馆藏

日期分布

学科分类号

  • 1 篇 理学
    • 1 篇 物理学
  • 1 篇 工学
    • 1 篇 电气工程

主题

  • 1 篇 oscillators
  • 1 篇 sequential circu...
  • 1 篇 logic gates
  • 1 篇 noise
  • 1 篇 time frequency a...
  • 1 篇 performance fluc...
  • 1 篇 sequential logic...
  • 1 篇 circuit matrix a...
  • 1 篇 low voltage
  • 1 篇 random telegraph...
  • 1 篇 frequency conver...
  • 1 篇 low voltage oper...
  • 1 篇 cmos logic circu...
  • 1 篇 delay
  • 1 篇 size 65 nm

机构

  • 1 篇 kyoto inst techn...
  • 1 篇 kyoto univ kyoto...
  • 1 篇 jst crest

作者

  • 1 篇 kobayashi kazuto...
  • 1 篇 ito kyosuke
  • 1 篇 nishizawa shinic...
  • 1 篇 matsumoto takash...
  • 1 篇 sunagawa hiroki
  • 1 篇 onodera hidetosh...

语言

  • 1 篇 英文
检索条件"主题词=circuit matrix array"
1 条 记 录,以下是1-10 订阅
The Impact of RTN on Performance Fluctuation in CMOS Logic circuits
The Impact of RTN on Performance Fluctuation in CMOS Logic C...
收藏 引用
49th Annual IEEE International Reliability Physics Symposium (IRPS)
作者: Ito, Kyosuke Matsumoto, Takashi Nishizawa, Shinichi Sunagawa, Hiroki Kobayashi, Kazutoshi Onodera, Hidetoshi Kyoto Univ Kyoto 6068501 Japan Kyoto Inst Technol Kyoto 6068585 Japan JST CREST Tokyo Japan
In this paper, the impact of Random Telegraph Noise (RTN) on CMOS logic circuits observed in a circuit matrix array is reported. We discuss the behavior of RTN under circuit operation, and reveal that the impact of RT... 详细信息
来源: 评论