With the growing number of process variation (PV) sources in deeply nano-scaled technologies, parameterized device and circuitmodeling is becoming very important for chip design and verification. However, the high di...
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With the growing number of process variation (PV) sources in deeply nano-scaled technologies, parameterized device and circuitmodeling is becoming very important for chip design and verification. However, the high dimensionality of parameter space, for PV analysis, is a serious modeling challenge for emerging VLSI technologies. These parameters correspond to various interdie and intradie variations, and considerably increase the difficulties of design validation. Today's response surface models and most commonly used parameter reduction methods, such as principal component analysis and independent component analysis, limit parameter reduction to linear or quadratic form and they do not address the higher order of nonlinearity among process and performance parameters. In this paper, we propose and validate a feature selection method to reduce the circuitmodeling complexity associated with high parameter dimensionality. This method relies on a learning-based nonlinear sparse regression, and performs a parameter selection in the input space rather than creating a new space. This method is capable of dealing with mixed Gaussian and non-Gaussian parameters and results in a more precise parameter selection considering statistical nonlinear dependencies among input and output parameters. The application of this method is demonstrated in digital circuit timing analysis in both FinFET and Silicon Nanowire technologies. The results confirm the efficiency of this method to significantly reduce the number of required simulations while keeping estimation error small.
In this paper the spurious free dynamic range (SFDR) of a current steering digital-to-analog converter (DAC) is related to the process parameters used for its implementation. It is shown that the realization of such D...
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ISBN:
(纸本)9781467330213
In this paper the spurious free dynamic range (SFDR) of a current steering digital-to-analog converter (DAC) is related to the process parameters used for its implementation. It is shown that the realization of such DACs in advanced processes provides power and area reduction combined with faster signaling. However, it is very challenging to improve the SFDR at a certain given output swing and sampling frequency. It is demonstrated that the SFDR can be doubled by using an optimized cascode switch. It is also concluded that compared to MOSFET based approaches higher sampling frequencies can be achieved by bipolar transistor based DACs if the SFDR and transition frequency are fixed. The reason is the higher Early voltage of bipolar transistors.
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