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Conference on Languages, Compilers and Tools for Embedded Systems

作者： Chu, Michael L. Mahlke, Scott A. Univ Michigan Adv Comp Architecture Lab Ann Arbor MI 48109 USA

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ISBN: (纸本)9781595936325

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关键词： algorithms experimentation performance code and data partitioning fine-grain parallelism multicore compilation

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code and data partitioning for fine-grain parallelism

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ACM SIGPLAN NOTICES 2007年第7期42卷 161-163页

作者： Chu, Michael L. Mahlke, Scott A. Univ Michigan Adv Comp Architecture Lab Ann Arbor MI 48109 USA

A study was conducted to demonstrate an alternative compiler-directed method for program parallelization by exploiting fine-grain instruction-level parallelism (ILP). The fine-grain method used an additional dimension to increase performance and exploit the multiple underlying cores. The study focused on compiling to chip-multiprocessors, such as RAW that exploited TLP and ILP. The main problem to be solved was related to creating an intelligent partitioning of TLP and ILP data in the application and executing computation operations. A phase-ordered approach was proposed to partition the data and the computation in the code. The data access partition was used to drive the partitioning of the remaining the code, while the approach profiled the program to determine statistics about each memory operation, such as its affinity towards other operations and an estimated working set size.

关键词： algorithms experimentation performance code and data partitioning fine-grain parallelism multicore compilation

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code and data structure partitioning for parallel and flexible MPSoC specification using designer-controlled recoding

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2008年第6期27卷 1078-1090页

作者： Chandraiah, Pramod Doemer, Rainer Univ Calif Irvine Irvine CA 92697 USA

MultiProcessor Systems-on-Chip (MPSoCs) are increasingly being used to build efficient and cost-effective embedded systems that meet the necessary real-time requirements. However, programming heterogeneous MPSoCs is highly challenging. The existing automatic parallelizing techniques, although effective on homogeneous shared-memory architectures, are insufficient for MPSoCs, which are typically characterized by heterogeneous processing elements and memory architectures. The lack of effective automatic techniques for recoding and parallelization requires designers to manually partition the code and the data structures in the reference application to generate a parallel and flexible specification model. Such manual algorithm partitioning by the designer is time consuming and error prone. In this paper, we motivate the need for automation in system specification and present a novel designer-controlled approach to recode applications written in a C-based System-Level Description Language. We present six automated source code transformations that, under the control of the designer, automatically partition and reorganize code and data structures to create a parallel and flexible abstract specification model that can be mapped onto a heterogeneous MPSoC using a top-down system-level design flow. Our experimental results show significant productivity gains and quality improvements in the end design.

关键词： code and data partitioning design automation multi-processor systems-on-chip recoding source code transformation system level design

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