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Dynamic code compression for JavaScript engine

SOFTWARE-PRACTICE & EXPERIENCE 2023年第5期53卷 1196-1217页

作者： Park, Hyukwoo Kim, Seonghyun Bae, Boram Samsung Res Samsung Elect Seoul South Korea

Web applications created using web languages such as HTML, CSS, and JavaScript are widely used regardless of execution environments, owing to their portability and popularity. Since JavaScript language is conventionally used for complex computations in large-scale web apps, many optimization techniques have been proposed to accelerate the JavaScript performance. However, most of these optimizations speed up JavaScript engines at the expense of consuming more memory. Hence, memory consumption becomes an additional concern in the JavaScript field. Based on the research on memory status, we unearthed that a substantial portion of the heap memory is allocated for JavaScript source code, particularly in lightweight JavaScript engines, which may range from 13.2% to a maximal 52.5% of the entire heap. To resolve this memory issue, this article suggests a new memory optimization method, called dynamic code compression that dynamically compresses the source code and keeps its compressed form instead of the source string. A novel heuristic is proposed to timely compress the source code. We also re-design the internal structure of the JavaScript engine to efficiently compress the source code without incurring any conflict. Using our code compression method, we could reduce the entire heap memory by up to 43.3% and consistently downsize the overall heap size. From an evaluation of standard benchmarks, our approach showed just 2.7% degradation in performance with negligible compression overhead, proving the feasibility of the code compression technique.

关键词： code compression JavaScript memory optimization web engine

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Programmable Dictionary code compression for Instruction Stream Energy Efficiency 38

Programmable Dictionary Code Compression for Instruction Str...

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38th IEEE International Conference on Computer Design (ICCD)

作者： Multanen, Joonas Hepola, Kari Jaaskelainen, Pekka Tampere Univ Fac Informat Technol & Commun Sci ITC Tampere Finland

ISBN: (纸本)9781728197104

We propose a novel instruction compression scheme based on fine-grained programmable dictionaries. In its core is a compile-time region-based control flow analysis to selectively update the dictionary contents at runtime, minimizing the update overheads, while maximizing the beneficial use of the dictionary slots. Unlike in the previous work, our approach selects regions of instructions to compress at compile time and changes dictionary contents in a fine-grained manner at runtime with the primary goal of reducing the energy footprint of the processor instruction stream. The proposed instruction compression scheme is evaluated using RISC-V as an example instruction set architecture. The energy savings are compared to an instruction scratch pad and a filter cache as the next level storage. The method reduces instruction stream energy consumption up to 21% and 5.5% on average when compared to the RISC-V C extension with a 1% runtime overhead and a negligible hardware overhead. The previous state-of-the-art programmable dictionary compression method provides a slightly better compression ratio, but induces about 30% runtime overhead.

关键词： code compression dictionary compression energy efficiency energy optimization instruction fetch instruction stream

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A Space- and Energy-Efficient code compression/Decompression Technique for Coarse-Grained Reconfigurable Architectures

A Space- and Energy-Efficient Code Compression/Decompression...

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IEEE/ACM International Symposium on code Generation and Optimization (CGO)

作者： Egger, Bernhard Lee, Hochan Kang, Duseok Moghaddam, Mansureh S. Cho, Youngchul Lee, Yeonbok Kim, Sukjin Ha, Soonhoi Choi, Kiyoung Seoul Natl Univ Seoul South Korea Samsung Elect Seoul South Korea

ISBN: (纸本)9781509049318

We present an effective code compression technique to reduce the area and energy overhead of the configuration memory for coarse-grained reconfigurable architectures (CGRA). Based on a statistical analysis of existing code, the proposed method reorders the storage locations of the reconfigurable entities and splits the wide configuration memory into a number of partitions. code compression is achieved by removing consecutive duplicated lines in each partition. Compressibility is increased by an optimization phase in the compiler. The optimization minimizes the number of configuration changes for individual reconfigurable entities. Decompression is performed by a simple hardware decoder logic that is able to decode lines with no additional latency and negligible area overhead. Experiments with over 190 loop kernels from different application domains show that the proposed method achieves a memory reduction of over 40% on average with four partitions. The compressibility of yet unseen code is only slightly lower with 35% on average. In addition, executing compressed code results in a 22 to 47% reduction in the configuration logic's energy consumption.

关键词： Coarse-grained reconfigurable architecture code compression energy reduction

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Clustered Multi-dictionary code compression Method for Portable Medical Electronic Systems 19

Clustered Multi-dictionary Code Compression Method for Porta...

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19th Annual IEEE International Conference on e-Health Networking, Applications and Services (Healthcom)

作者： Tu, Ji Yu, Xiangyi Li, Yangyang Yuan, Liu Li, Meng Fang, Weiwei China Acad Elect & Informat Technol Innovat Ctr Beijing 100041 Peoples R China Beijing Jiaotong Univ Sch Comp & Informat Technol Beijing 100044 Peoples R China

ISBN: (纸本)9781509067046

Currently, the demand on portable medical electronic systems are increasing, for they provide services and information to both patients and doctors that the traditional medical methods cannot achieve. However, the development of portable medical electronic systems has many limitations, i.e., one has to find a sweet spot among performance, power consumption, size, and cost. For instance, if one only increases the memory of a system, not only does the cost go up, the power consumption also goes up, meanwhile the standby time goes down. In some cases, the hardware size goes up as well. One way of satisfying these constraints while retaining the design and functionality is to compress executable code and data as much as possible. In this paper, a novel clustered multi-dictionary code compression method is proposed to effectively reduce the memory size by replacing the most common codes with shorter codeword. The codes are clustered according to their repeating times. Each cluster is compressed with a different dictionary to make the codeword length different. By pairing clusters and dictionaries with the highest entropy, the compression efficiency becomes the best. Theoretical analysis and experimental results show that this method can achieve significant compression effect. The code of MiBench benchmark compiled under ARM and MIPS instruction set architecture are compressed with this method and the code size decreases by 50%. Aside from high compression ratio, our method also provides relatively fast encoding and very fast decoding.

关键词： portable medical electronic systems code compression multi-dictionary cluster

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code compression using Huffman and Dictionary-based Pattern Blocks

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IEEE LATIN AMERICA TRANSACTIONS 2015年第7期13卷 2314-2321页

作者： Dias, W. R. A. Moreno, E. D. Inst Fed Sergipe Coordenadoria Informat COINF Itabaiana Sergipe Brazil Univ Fed Sergipe Dept Comp DComp Sao Cristovao Sergipe Brazil

This paper presents a new code compression method where we merge the Huffman algorithm with the formation of patterns of blocks, which are found into the dictionary. We seek two consecutive blocks in two levels, one of them into compressed code and the other related to uncompressed code. We have used simulation with SimpleScalar and programs from MiBench. Our proposal has achieved a compression rate of 34.5% and 7% improvement in code compression when compared to the Huffman traditional method.

关键词： code compression Embedded Systems Huffman Dictionary-based Pattern Blocks MiBench

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A Novel Classified Multi-dictionary code compression for Embedded Systems 27

A Novel Classified Multi-dictionary Code Compression for Emb...

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27th Chinese Control and Decision Conference (CCDC)

作者： Tu, Ji Zheng, MeiSong Li, Lijian Chinese Acad Sci Inst Automat Beijing 100190 Peoples R China China Elect Technol Grp Corp Chinese Acad Elect & Informat Technol Beijing Peoples R China

ISBN: (纸本)9781479970162

This paper present a novel code compression method using classified multi-dictionary, which significantly improves the compression efficiency without introducing any decompression penalty. Our classified multi-dictionary code compression method separates the executable binary code into different classes, and each class of the binary code is compressed using its own dictionary and codeword. We use shorter codeword for the class which its binary code occurs more frequently than the frequency of the binary code in other classes. The appropriate classes are found to make sure that the compression efficiency is the best. Experimental results of MiBench benchmark for ARM show that a significant degree of compression can be achieved. Our approach outperforms the existing variance code compression techniques by an average of 15%, giving a compression ratio of 50%similar to 55%. The impact on system performance is slight and for some memory implementations the reduced memory bandwidth actually increases performance.

关键词： code compression Multi-dictionary Classify Embedded System

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A Novel Clustered Multi-dictionary code compression Method 5

A Novel Clustered Multi-dictionary Code Compression Method

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2015 5th International Conference on Electronics Information and Emergency Communication (ICEIEC)

作者： Tu, Ji Zheng, Meisong Li, Lijian Chinese Acad Sci Inst Automat Beijing 100190 Peoples R China China Elect Technol Grp Corp Chinese Acad Elect & Informat Technol Beijing 100041 Peoples R China

ISBN: (纸本)9781479972845

code compression is traditionally used to reduce the code size by compressing the codes with higher static frequency. A novel clustered multi-dictionary code compression method is proposed to effectively reduce the memory size which program code stored. We cluster the code set according to the repeat times frequency of different codes in it. Each cluster is compressed with different dictionary and the codeword of each cluster is different. We use shorter codeword to point to the more frequently occurred codes in cluster. By finding the best clusters, the entropy of clustered multi-dictionary code is high and the compression efficiency is the best. Theoretical proof and experimental results show that the compression effect of this method is significant. code of MiBench benchmark compiled under ARM and MIPS instruction set architecture are compressed with this method and the best compression ratio is 50%.

关键词： code compression Multi-dictionary Cluster Embedded System

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Studying the code compression design space - A synthesis approach

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JOURNAL OF SYSTEMS ARCHITECTURE 2014年第2期60卷 179-193页

作者： Menon, Sreejith K. Mathworks Natick MA 01760 USA

Embedded domain has witnessed the application of different code compression methodologies on different architectures to bridge the gap between ever-increasing application size and scarce memory resources. Selection of a code compression technique for a target architecture requires a detailed study and analysis of the code compression design space. There are multiple design parameters affecting the space, time, cost and power dimensions. Standard approaches of exploring the code compression design space are tedious, time consuming, and almost impractical with the increasing number of proposed compression algorithms. This is one of the biggest challenges faced by an architect trying to adopt a code compression methodology for a target architecture. We propose a novel synthesis based tool-chain for fast and effective exploration of the code compression design space and for evaluation of the tradeoffs. The tool-chain consists of a frontend framework that works with different compression/decompression schemes and a backend with high-level-synthesis, logic-synthesis, and power estimation tools to output the critical design parameters. We use the tool-chain to effectively analyze different code compression/decompression schemes of varying complexities. (C) 2013 Elsevier B.V. All rights reserved.

关键词： code compression High level synthesis Logic synthesis Power estimation Embedded systems

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Energy-efficient instruction compression with programmable dictionaries

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DESIGN AUTOMATION FOR EMBEDDED SYSTEMS 2024年第3-4期28卷 245-274页

作者： Multanen, Joonas de Bruin, Barry Corporaal, Henk Jaaskelainen, Pekka Tampere Univ Tampere Finland Eindhoven Univ Technol Eindhoven Netherlands

To improve the energy efficiency of computation, accelerators trade off performance and energy consumption for flexibility. Fixed-function accelerators reach high energy efficiency, but are inflexible. Adding programmability via an instruction set architecture (ISA) incurs an energy consumption overhead, as instructions are fetched and decoded. To reduce it, hardware-controlled instruction caches and software-controlled components, such as loop buffers and (programmable) dictionaries improve the energy efficiency of instruction streams in embedded processors. Reducing the instruction overhead with code compression is well established and dictionary compression has been an effective approach due to its simplicity. Compared to static dictionaries, adding programmability improves the effectiveness. However, run-time-programmable dictionary compression and its effect on energy consumption has not been thoroughly studied. We describe a scheme to target energy efficiency by using fine-grained programmable dictionaries in embedded compute devices. Guided by compile-time analysis, the dictionary contents are changed during execution. On CHStone and Embench suites, our method reduces energy consumption on average by 11.4% and 3.8% with negligible run-time overhead. The addition of a loop buffer further reduces the energy consumption by 19.8% and 4.5% in the two suites. Our results indicate that programmable dictionary compression allows further energy reductions over an already highly tuned instruction stream.

关键词： code compression Computer architecture Embedded systems Energy efficiency RISC-V VLIW

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A Novel Proposal for a Standalone Compressor and Decompressor Hardware Module from ISA

A Novel Proposal for a Standalone Compressor and Decompresso...

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IEEE Latin American Electron Devices Conference (LAEDC)

作者： Sanabria-Villalobos, Esteban A. Chavarria-Zamora, Luis A. Araya-Martinez, Leonardo Tecnol Costa Rica Comp Engn Dept Cartago Costa Rica

ISBN: (数字)9781665497671

ISBN: (纸本)9781665497671

Rapidly evolving markets and growing demand of digital application by consumers, along with hardware long time-to-market and rising manufacturing costs, are pushing the market towards software-based development, directly increasing power, area and memory requirements of current computer systems. Efforts to reduce this growing demand on storage devices are multiple, among them are assembly code compression and decompression techniques, which reduce the memory footprint of programs, thus reducing the resources and costs necessary for their elaboration. For this reason, is proposed a digital design and implementation of a real-time assembly code decompression module, that works under the demand of a processor, which is independent of the ISA, does not require modifications of the processing systems and reduce the amount of memory needed. The proposed microarchitecture is capable of decompress code in real-time, as well the results of the evaluation of the module, consisting of a 32-bit ARM processor and memory holding the compressed instructions, show the adaptability of the module to different ISA and processors using just their common inputs and outputs.

关键词： ARM Sequitur algorithm code compression dictionary compression real-time decompression DSP design HDL validation verification

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