Single-pixel Passive Millimeter Wave (PMMW) imaging system has drawn much attention for its low cost and low complexity. Nowadays, researchers put more effort into the study of the single-pixel PMMW imaging technology...
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ISBN:
(纸本)9781538616208
Single-pixel Passive Millimeter Wave (PMMW) imaging system has drawn much attention for its low cost and low complexity. Nowadays, researchers put more effort into the study of the single-pixel PMMW imaging technology as the wide application of Compressive Sensing technology. Previous studies have indicated that the key of the single-pixel imaging technology is the design of coding template. In most studies, a large number of single-templates are applied for coding sampling. These kinds of methods are not suitable for engineering applications due to their low imaging speed. Therefore, a coding method based on quasi cyclic S matrix is proposed, and a novel coding template is designed to improve the imaging speed in this paper. The algorithms of OMP and TVAL3 simulation results in MATLAB verify the effectiveness of the proposed method.
The concept of Parallel Vector (scratch pad) Memories (PVM) was introduced as one solution for Parallel Computing in DSP, which can provides parallel memory addressing efficiently with minimum latency. The parallel pr...
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The concept of Parallel Vector (scratch pad) Memories (PVM) was introduced as one solution for Parallel Computing in DSP, which can provides parallel memory addressing efficiently with minimum latency. The parallel programming more efficient by using the parallel addressing generator for parallel vector memory (PVM) proposed in this thesis. However, without hiding complexities by cache, the cost of programming is high. To minimize the programming cost, automatic parallel memory address generation is needed to hide the complexities of memory *** thesis investigates methods for implementing conflict-free vector addressing algorithms on a parallel hardware structure. In particular, match vector addressing requirements extracted from the behaviour model to a prepared parallel memory addressing template, in order to supply data in parallel from the main memory to the on-chip vector *** to the template and usage of the main and on-chip parallel vector memory, models for data pre-allocation and permutation in scratch pad memories of ASIP can be decided and configured. By exposing the parallel memory access of source code, the memory access flow graph (MFG) will be generated. Then MFG will be used combined with hardware information to match templates in the template library. When it is matched with one template, suited permutation equation will be gained, and the permutation table that include target addresses for data pre-allocation and permutation is created. Thus it is possible to automatically generate memory address for parallel memory accesses.A tool for achieving the goal mentioned above is created, Permutator, which is implemented in C++ combined with XML. Memory access coding template is selected, as a result that permutation formulas are specified. And then PVM address table could be generated to make the data pre-allocation, so that efficient parallel memory access is *** result shows that the memory access complexities is hiden by u
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