Traditionally, increasing logical masking probability has been used to improve the circuit reliability against single-event transients (SETs). As the very first work, this paper presents a new approach to increase the...
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Traditionally, increasing logical masking probability has been used to improve the circuit reliability against single-event transients (SETs). As the very first work, this paper presents a new approach to increase the reliability of digital circuits against soft errors caused by multiple event transients (METs) by taking advantages of circuit partitioning and local logical restructuring techniques. In the proposed approach, the circuit is partitioned into various subcircuits and, then, several structures of each subcircuits which satisfy the area constraints are extracted by using a graph-based procedure. In order to select the suitable alternative between various subcircuit structures, we introduce a novel metric named global failure probability in the presence of METs (GFPM). This parameter provides an evaluation of each subcircuits contribution in the soft error rate (SER) of the given circuit making it possible to estimate the impacts of changing the structure of the subcircuits on the circuit SER. Hence, it prevents from repeatedly calculating the SER of the circuit that is very time-consuming leading to significant improvements in the optimization runtime. Experimental studies on ISCAS benchmark circuits show that the proposed approach, on average, achieves 18.4% SER reduction with 11.9% area overhead and 8.2% delay overhead comparing to the original circuit while the global SET-based SER mitigation approach and the global MET-based SER mitigation approach achieve 8.46% and 21.8% SER reduction, respectively. Besides, the proposed technique is about $580 \times $ faster than the global MET-based method.
On the basis of EST (Equivalent STate hashing) algorithm, this paper researches a kind of test generation algorithm based on search state dominance for combinational circuit. According to the dominance relation of the...
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On the basis of EST (Equivalent STate hashing) algorithm, this paper researches a kind of test generation algorithm based on search state dominance for combinational circuit. According to the dominance relation of the E-frontier (evaluation frontier), we can prove that this algorithm can terminate unnecessary searching step of test pattern earlier than the EST algorithm through some examples, so this algorithm can reduce the time of test generation. The test patterns calculated can detect faults given through simulation.
Testing of VLSI circuits can cause generation of excessive heat which can damage the chips under test. In the random testing environment, high-performance CMOS circuits consume significant dynamic power during testing...
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ISBN:
(纸本)0780393635
Testing of VLSI circuits can cause generation of excessive heat which can damage the chips under test. In the random testing environment, high-performance CMOS circuits consume significant dynamic power during testing because of enhanced switching activity in the internal nodes. Our work focuses on the fact that power minimization is a Traveling Salesman Problem (TSP). We explore application of local search and genetic algorithms to test set reordering and perform a quantitative comparison to previously used deterministic techniques. We also consider reduction of the original test set as a dual-objective optimization problem, where switching activity and fault coverage are the two objective functions.
Constructing testability functions of a combinational circuit line, such as: the controllability, observability and stuck-at fault detection functions, as well as the complement of the observability function is consid...
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ISBN:
(纸本)9781728185040
Constructing testability functions of a combinational circuit line, such as: the controllability, observability and stuck-at fault detection functions, as well as the complement of the observability function is considered. Methods and algorithms for constructing testability functions based on Binary Decision Diagram (BDD) and Disjunctive Normal Form (DNF), as well as methods for constructing Conjunctive Normal Form (CNF) and obtaining testability functions using a SAT solver are proposed. Methods and algorithms for constructing testability functions for all and a subset of lines of a circuit are also proposed. Proposed methods and algorithms make it possible to significantly reduce the computational costs for constructing testability functions of a combinational circuit.
In this paper the structure-based test generation algorithm has been studied for the problem that test patterns are obtained by determined finite faults set in the past. This Algorithm can find out all test patterns o...
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In this paper the structure-based test generation algorithm has been studied for the problem that test patterns are obtained by determined finite faults set in the past. This Algorithm can find out all test patterns one tithe, so faults detection is very convenient. By simulation, the smallest test patterns set can be obtained and faults coverage rate is 100%.
Prime faults are introduced for the study of multiple fault diagnosis in combinational circuits. It is shown that every multiple fault in a network can be represented by a functionally equivalent fault with prime Faul...
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Prime faults are introduced for the study of multiple fault diagnosis in combinational circuits. It is shown that every multiple fault in a network can be represented by a functionally equivalent fault with prime Faults as its only components. Masking and covering relations among faults are defined and used to significantly simplify multiple fault analysis and test generation. An efficient algorithm that generates a multiple fault detection test set and identifies any redundancy is presented. Suggestions for designing networks to yield a minimum number of tests in the multiple fault detection test set are included.
A single bridging fault location technique for CMOS combinational circuits is proposed. In this technique, the cause of an error observed at the primary outputs is deduced using a diagnosis table constructed from the ...
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A single bridging fault location technique for CMOS combinational circuits is proposed. In this technique, the cause of an error observed at the primary outputs is deduced using a diagnosis table constructed from the circuit under test and the given tests. The size of a diagnosis table is [the number of gates] X [the number of tests] X2 bits, which is much smaller than that of the fault dictionary. The experimental results show that the number of possible bridging faults is reduced to less than 5 in several seconds, when using the tests to detect single stuck-at faults and considering only the bridging faults between physically adjacent nets.
In our previous paper [9] we presented a path-tracing method of multiple gate delay fault diagnosis in combinational circuits. In this paper, we propose an improved method that uses the ambiguous delay model. This del...
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In our previous paper [9] we presented a path-tracing method of multiple gate delay fault diagnosis in combinational circuits. In this paper, we propose an improved method that uses the ambiguous delay model. This delay model makes provision for parameter variations in the manufacturing process of ICs. For the effectiveness of the current method, we propose a timed 8-valued simulation and some new diagnostic rules. Furthermore, we introduce a preparatory process that speeds up diagnosis. Also, at the end of diagnosis, additional information from the results of the preparatory process makes it possible to distinguish between non-existent faults and undiagnosed faults.
In this paper, a resynthesis technique is introduced in order to reduce the Soft Error Rate (SER) of combinational circuits. This technique is based on the circuit partitioning and a local logical replacement. The pro...
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In this paper, a resynthesis technique is introduced in order to reduce the Soft Error Rate (SER) of combinational circuits. This technique is based on the circuit partitioning and a local logical replacement. The proposed method provides an innovative approach to maximize the logical masking probability of the circuit gates. In this technique, the circuit is divided into a set of small sub-circuits. Different logical implementations of sub-circuits with the same function which satisfy the circuit timing and area constraints are carried out using a AND-INV Graph (AIG) scheme. Then, an implementation of each sub-circuit that provides the maximum logical masking and minimum transient faults generation probability is used in place of the current sub-circuit in the main circuit. In order to choose the best alternative among the different implementations of a sub-circuit (i.e. the one that provides the maximum circuit SER reduction), a new metric called Global Failure Probability (GFP) is introduced. The proposed parameter evaluates the contribution of different implementations of sub-circuits in total circuit SER. Using GFP to assess the effect of different implementations of a sub-circuit in the circuit SER avoids estimating the total circuit SER repeatedly during SER optimization process that is very time consuming. Simulation results based on ISCAS benchmark circuits show that, on average, a circuit failure reduction of 23.4% is achieved compared to the original one;where the average area overhead and delay overhead is 8.72% and 5.63% of the original circuit, respectively. The results also show that the proposed method is 77.8x faster compared to simulation based method [6].
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