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6th Symposium on Optoelectronics (SIOEL'99)

作者： Schiopu, P Degeratu, V Degeratu, S Politehnica Univ Bucharest Bucharest Romania

ISBN: (纸本)0819437050

In actual systems the optic signal are detected, processed and electronic recorded. These hybrid systems diminish considerably the processing speed of optical signals. So, it's absolute necessary to implement the processing signals of optic systems which have to be competitive with the actual electronic systems. In this paper, the authors present from theoretical point of view, the realization of some logical gates (AND, OR, NOT) with photonic devices and combinational logic circuits with photonic devices as decoder, demultiplexer and multiplexer.

关键词： combinational logic circuits logical circuits with photonic devices optical logic circuits optical computer

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Graph-theoretic algorithm for finding maximal supergates in combinational logic circuits

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IEE PROCEEDINGS-circuits DEVICES AND SYSTEMS 1996年第6期143卷 313-318页

作者： Min, HB Park, ES HANYANG UNIV DEPT ELECT ENGN ANSAN 425791 DYUNGGI DO SOUTH KOREA

Disjunctive decomposition of a large switching function into several smaller switching functions is an efficient way of solving many problems in logic design and testing areas. Finding disjunctive decomposition of an arbitrary switching function, however, is known to be a very difficult problem for which no practical solutions have been reported. Alternatively, a practical solution is to identify maximal supergates defined by Seth er al. (1985) which represent disjunctive decomposition of a logic circuit which realises a given switching function. An algorithm is presented which identifies maximal supergates in combinational logic circuits. The algorithm is based on both the graph-theoretic algorithms and the set manipulation algorithms such as depth-first search, biconnectivity and UNION/FIND. The time complexity of the algorithm is O(n + e), where n is the number of gates and e is the number of links between gates. Finally, the authors demonstrate experimental results of maximal supergates in ISCAS85 and ISCAS89 benchmark circuits.

关键词： combinational logic circuits graph-theoretic algorithms maximal supergates

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Comparative study of serial and parallel heuristics used to design combinational logic circuits

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OPTIMIZATION METHODS & SOFTWARE 2007年第3期22卷 485-509页

作者： Alba, Enrique Luque, Gabriel Coello Coello, Carlos A. Hernandez Lunat, Erika CINVESTAV IPN Evolut Computat Grp Secc Computac Dept Ing Elect Mexico City 07300 DF Mexico ETSI Informat Dept Lenguajes & Ciencias Computac Malaga 29071 Spain

In this article, we perform a comparative study of different heuristics used to design combinational logic circuits. This study mainly emphasizes the use of local search hybridized with a genetic algorithm (GA) and the impact of introducing parallelism. Our results indicate that a hybridization of a GA with a local search algorithm (simulated annealing) is beneficial and that the use of parallelism not only introduces a speedup in the algorithms compared (as expected) but also allows us to improve the quality of the solutions found.

关键词： combinational logic circuits genetic algorithms metaheuristics simulated annealing parallelization hybridization

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An Empirical Model for Predicting SE Cross Section for combinational logic circuits in Advanced Technologies

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE 2018年第1期65卷 304-310页

作者： Jiang, H. Zhang, H. Kauppila, J. S. Massengill, L. W. Bhuva, B. L. Vanderbilt Univ Dept Elect Engn & Comp Sci 221 Kirkland Hall Nashville TN 37235 USA

At the gigahertz range of frequencies, contribution of combinational logic upsets has increased significantly to the overall single-event (SE) upset rate (SER) of sequential circuits. Most approaches for modeling and/or predicting logic SER are either pure simulation based or pure experiment based. Simulation-based approaches need a lot of computing power. Experiment-based approaches require fabrication of actual circuits. This paper presents an empirical method that uses experimental data from simple test structures for estimating SE vulnerability of any combinational logic circuit. Estimated logic SEU cross section matches well with the measured logic SEU cross section. Estimated logic SEU cross section results obtained with the proposed method are within 2x average error when compared to the experimentally measured logic SEU cross section. This method only needs to be calibrated once for use at a given technology node.

关键词： combinational logic circuits cross section FinFET single-event (SE) upset rate (SER)

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Design of Memristor-Based combinational logic circuits

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circuits SYSTEMS AND SIGNAL PROCESSING 2021年第12期40卷 5825-5846页

作者： Liu, Gongzhi Shen, Shuhang Jin, Peipei Wang, Guangyi Liang, Yan Hangzhou Dianzi Univ Inst Modern Circuits & Intelligent Informat Hangzhou 310018 Peoples R China

This paper proposes three modified memristor ratioed logic (MRL) gates: NOT, NOR and A AND (NOR B) (i.e., A center dot (B) over bar), each of which only needs 1 memristor and 1 NMOS. Based on the modified MRL gates, we design some combinational logic circuits, including 1-bit comparator, 3-bit binary encoder, 3-bit binary decoder and 4:1 multiplexer. Furthermore, an improved multifunctional logic module is proposed, which contains one NMOS transistor and five memristors, and can implement AND, OR and XOR logic operations. Using this multifunctional logic module, a 4-bit comparator and a 1-bit full adder are designed. Finally, the proposed combinational logic circuits are verified by LTSPICE simulations. Compared with other memristor-based logic circuits and the traditional CMOS technology, the proposed logic circuits have made great progress in reducing delay, power consumption and the number of transistors.

关键词： Memristor Digital logic circuits combinational logic circuits

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MULTIPLE FAULT DETECTION FOR combinational logic circuits

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IEEE TRANSACTIONS ON COMPUTERS 1975年第3期C 24卷 233-242页

作者： YAU, SS YANG, SC NORTHWESTERN UNIV BIOMED ENGN CTR EVANSTON IL 60201 USA NORTHWESTERN UNIV DEPT COMP SCI & ELECT ENGN EVANSTON IL 60201 USA

An algorithm for generating test sets to detect all the multiple stuck-at-faults in combinational logic circuits is presented. This algorithm generates a test set using a set of functions, called representative functions, which consists of much fewer functions than all possible multiple stuck-at fault functions, but is sufficient for test generation. Two different methods of finding such a set of representative functions are presented. The test sets derived from the set of representative functions obtained by the first method will be smaller than that by the second method, but the second method is much simpler than the first especially for highly redundant circuits. Nevertheless, the complexity of this algorithm using the first method is about the same as that of Bossen and Hong"s algorithm which is the simplest existing algorithm under the multiple stuck-at fault assumption, and yet the number of tests in a test set generated will always be smaller for redundant circuits and the same for irredundant circuits as that generated by Bossen and Hong"s algorithm for irredundant circuits.

关键词： Algorithms combinational logic circuits fault detections fault functions multiple stuck-at faults redundant circuits representative sets.

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Delay abstraction in combinational logic circuits

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED circuits AND SYSTEMS 1997年第10期16卷 1205-1212页

作者： Kobayashi, N Malik, S NEC Corp Ltd C&C Media Res Labs Kawasaki Kanagawa 216 Japan Princeton Univ Dept Elect Engn Princeton NJ 08544 USA

In this paper we propose a data structure for abstracting the delay information of a combinatorial circuit. The particular abstraction that we are interested in is one that preserves the delays between all pairs of inputs and outputs in the circuit. Such abstractions are useful when considering the delay of cascaded circuits in high-level synthesis and other such applications in synthesis, The proposed graphical data structure is called the concise delay network, and is of size proportional to (m + n) in best case, where m and rr refer to the number of inputs and outputs of the circuit. In comparison, a delay matrix that stores the maximum delay between each input-output pair has size proportional to m x n. For circuits with hundreds of inputs and outputs, this storage and the associated computations become quite expensive, especially when they need to be done repeatedly during synthesis. We present heuristic algorithms for deriving these concise delay networks, Experimental results shows that, in practice, we can obtain concise delay network with the number of edges being a small multiple of (m + n).

关键词： combinational logic circuits data structures delay estimation directed graphs

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TRANSITION COUNT TESTING OF combinational logic-circuits

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IEEE TRANSACTIONS ON COMPUTERS 1976年第6期25卷 613-620页

作者： HAYES, JP UNIV SO CALIF DEPT ELECT ENGNLOS ANGELESCA 90007 UNIV SO CALIF SERV COMP SCILOS ANGELESCA 90007

logic circuits are usually tested by applying a sequence of input patterns S to the circuit under test and comparing the observed response sequence R bit by bit to the expected response Ro. The transition count (TC) of R, denoted c(R), is the number of times the signals forming R change value. In TC testing c(R) is recorded rather than R. A fault is detected if the observed TC c(R) differs from the correct TC c(Ro). This paper presents a formal analysis of TC testing. It is shown that the degree of detectability and distinguishability of faults obtainable by TC testing is less than that obtainable by conventional testing. t is argued that the TC tests should be constructed to maximize or minimize c(Ro). General methods are presented for constructing complete TC tests to detect both single and multiple stuck-line faults in combinational circuits. Optimal or near-optimal test sequences are derived for one-and two-level circuits. The use of TC testing for fault location is examined, and it is concluded that TC tests are relatively inefficient for this purpose.

关键词： combinational logic circuits fault detection fault diagnosis minimal test sets test generation transition count (TC) testing.

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On Heuristics for Seeding the Initial Population of Cartesian Genetic Programming Applied to combinational logic circuits

On Heuristics for Seeding the Initial Population of Cartesia...

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Genetic and Evolutionary Computation Conference (GECCO)

作者： Manfrini, Francisco A. L. Bernardino, Heder S. Barbosa, Helio J. C. Univ Fed Juiz de Fora Juiz de Fora MG Brazil IFET Juiz De Fora MG Brazil LNCC Petropolis RJ Brazil

ISBN: (纸本)9781450343237

The design of circuits is an important research field and the corresponding optimization problems are complex and computationally expensive. Here, a Cartesian Genetic Programming (CGP) technique was used to design combinational logic circuits. Several configurations were tested for seeding the initial population. First, the number of rows, columns, and levels-back were varied. In addition, the initial population was generated using only NAND gates. These configurations were compared with results from the literature in four benchmark circuits, where in all instances it was possible to find that some seeding configurations contributed beneficially to the evolutionary process, allowing CGP to find a solution employing a lower number of fitness evaluations. Finally, the variation of the number of nodes of the individuals during the search was also analyzed and the results showed that there is a correlation between the topology of the initial population and the region of the search space which is explored.

关键词： Cartesian Genetic Programming population seeding combinational logic circuits

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Genetic Algorithm Based Design of combinational logic circuits using Reed Muller blocks

Genetic Algorithm Based Design of Combinational Logic Circui...

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World Congress on Engineering (WCE 2015)

作者： Vijayakumari, C. K. Mythili, P. James, Rekha K. Govt Engn Coll Rajiv Gandhi Inst Technol Dept Elect Engn Kottayam Kerala India Cochin Univ Sci & Technol Div Elect Kochi Kerala India

ISBN: (纸本)9789881925343

In this paper an approach based on an evolutionary algorithm to design combinational logic circuits with minimum number of Reed Muller units is suggested. Since replication of the same unit reduces the implementation cost of VLSI systems, a single control line Reed Muller universal logic module (RM ULM) alone is used for the design. Any Boolean function can be realized with this method using any optimization algorithm. Here Genetic Algorithm (GA) is used as the optimization tooL.A modification has been made on Davio decomposition technique and it has been observed that the circuits evolved are of lesser complexity and are superior to the circuits in traditional method in terms of power, area and delay.

关键词： combinational logic circuits Genetic Algorithm Reed Muller ULM Davio decomposition technique

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