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作者： Khawja Zaid Sikander University of Windsor

学位级别：硕士

With the continuous scaling of CMOS technologies, integrated circuits are becoming more sensitive to process variations and/or external factors such as temperature or background noise and, as a result, may operate unreliably. Circuit reliability can, however, be improved by making some design changes, and this requires an efficient and accurate method for evaluation of the reliability during the design stage. Reliability of a circuit can be estimated using either simulation-based or analytical based methods. While simulation-based methods (such as Monte-Carlo Simulation) can produce near to perfect estimated values, it takes a long time to run and the run-time increases exponentially with circuit size. On the other hand, analytical methods are relatively fast, but their accuracy level could decrease significantly if signal correlations are not properly accounted for. In this thesis, a new method for calculating the signal reliability correlation coefficient is presented. The proposed method takes advantage of the local information available in the circuit. It is assumed that all signal probabilities of error-free circuits are already available. The proposed method to calculate the Correlation Coefficient was tested for its efficiency and accuracy by applying it on large circuits in comparison with the results produced by the Monte-Carlo Simulation. For circuits containing thousands of gates, their output reliability and probability can be calculated using the proposed method within minutes, as opposed to over 10 hours using Monte-Carlo Simulation. The average errors are as low as 1.67% when all gate reliability is set at 0.95. Throughout the thesis, various ISCAS85 benchmark circuits have been tested under different conditions such as different gate reliabilities, input signal probability and input signal reliabilities in comparison with Monte-Carlo Simulation in order to verify its validity.

关键词： Circuit reliability analysis combinational logic circuits VLSI

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A weighted averaging method for signal probability of logic circuit combined with reconvergent fan-out structures

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Journal of Southeast University(English Edition) 2018年第2期34卷 173-181页

作者： Xiao Jie Ma Weifeng William Lee Shi Zhanhui College of Computer Science and Technology Zhejiang University of TechnologyHangzhou 310023China

By analyzing the structures of circuits,a novel approach for signal probability estimation of very large-scale integration(VLSI)based on the improved weighted averaging algorithm(IWAA)is *** the failure probability of the gate,first,the first reconvergent fan-ins corresponding to the reconvergent fan-outs were identified to locate the important signal correlation nodes based on the principle of homologous signal ***,the reconvergent fan-in nodes of the multiple reconverging structure in the circuit were identified by the sensitization path to determine the interference sources to the signal probability ***,the weighted signal probability was calculated by combining the weighted average approach to correct the signal ***,the reconvergent fan-out was quantified by the mixed-calculation strategy of signal probability to reduce the impact of multiple reconvergent fan-outs on the *** results on ISCAS85 benchmarks circuits show that the proposed method has approximate linear time-space consumption with the increase in the number of the gate,and its accuracy is 4.2%higher than that of the IWAA.

关键词： improved weighted averaging algorithm signal probability estimation gate error rate combinational logic circuits

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A METHOD OF SEARCH SPACE PRUNING BASED ON SEARCH STATE DOMINANCE

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SYSTEMS AND COMPUTERS IN JAPAN 1994年第4期25卷 1-12页

作者： FUJINO, T FUJIWARA, H School of Science and Technology Meijii University Kawasaki Japan 214 Members

EST (Equivalent STate hashing) algorithm, which reduces the search space form a different point of view from the conventional methods, was proposed for test generation by Giraldi and Bushnell. In this method the processes and results of the test pattern searches are stored and used to avoid fruitless searches to reduce the search space. In this paper the concept of search state equivalence, which is introduced for EST, is extended to that of search state dominance. Based on that concept an algorithm DST (Dominant STate hashing) is proposed. The search state dominance can prune the search space more effectively than the search state equivalence.

关键词： combinational logic circuits SEARCH SPACE PRUNING SEARCH STATE DOMINANCE SEARCH HISTORY TEST PATTERN GENERATION

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High-level area and power estimation for VLSI circuits

High-level area and power estimation for VLSI circuits

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IEEE International Conference on Computer-Aided Design

作者： Nemani Najm ECE Department and Coordinated Science Laboratory University of Illinois Urbana-Champaign Urbana IL USA

This paper addresses the problem of computing the area complexity of a multi-output combinational logic circuit, given only its functional description, i.e., Boolean equations, where area complexity is measured in terms of the number of gates required for an optimal multilevel implementation of the combinational logic. The proposed area model is based on transforming the given, multi-output Boolean function description into an equivalent single-output function. The model, is empirical, and results demonstrating its feasibility and utility are presented. Also, a methodology for converting the gate count estimates, obtained from the area model, into capacitance estimates is presented. High-level power estimates based on the total capacitance estimates and average activity estimates are also presented.

关键词： combinational logic circuits

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On estimation of fault efficiency for path delay faults

On estimation of fault efficiency for path delay faults

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Asian Test Symposium (ATS)

作者： Fukunaga Kajihara Takeoka Graduate School of Computer Science and System Engineering Kyushu Institute of Technology Japan Center for Microelectronics Systems Kyushu Institute of Technology Japan Semiconductor Company Matsushita Elecrric Indusrrial Company Limited Japan

In this paper, we propose a method to estimate fault efficiency for path delay faults based on untestable path analysis. In path delay fault testing, fault coverage of test patterns is usually, very low, because logic circuits often have huge number of paths including many untestable paths. Hence we should compute fault efficiency rather than fault coverage, but it is too difficult to compute exact fault efficiency in a short time, because there is no method to compute total number of untestable paths quickly. The proposed method statistically estimate the number of untestable paths based on untestable path analysis, and compute fault efficiency. Experimental results show that the proposed method can accurately estimate fault efficiency of given test patterns in a reasonable time.

关键词： logic circuit testing Fault diagnosis combinational logic circuits Sequential logic circuits Very-large-scale integration

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On average power dissipation and random pattern testability of CMOS combinational logic networks

On average power dissipation and random pattern testability ...

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IEEE International Conference on Computer-Aided Design

作者： Shen Ghosh Devadas Keutzer Massachusetts Institute of Technology Cambridge MA USA Mitubishi Electric Research Laboratories Sunnyvale CA USA Synopsys Inc. Mountain View CA USA

The implications of the observation that the probability of the occurrence of a transition on a wire of a circuit affects both the average power dissipation and the random pattern testability of a circuit are investigated. It is shown that restructuring a logic circuit can significantly affect its average power dissipation. Various methods for the synthesis of combinational logic networks are presented and the effect of different algorithms on the power dissipation of the circuit is demonstrated. The dual problem of improving the random pattern testability of logic circuits is emphasized. It is shown that modifying the signal probabilities can significantly affect the random pattern testability of a circuit.< >

关键词： CMOS integrated circuits combinational logic circuits Design automation logic circuit testing

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CRIS: A test cultivation program for sequential VLSI circuits

CRIS: A test cultivation program for sequential VLSI circuit...

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IEEE International Conference on Computer-Aided Design

作者： Saab Abraham Computer Engineering Research Center University of Texas Austin Austin TX USA

An approach to cultivating a test for combinational and sequential VLSI circuits described hierarchically at the transistor, gate, and higher levels is discussed. The approach is based on continuous mutation of a given input sequence and on analyzing the mutated vectors for selecting the test set. The approach uses a hierarchical simulation technique in the analysis to drastically reduce the memory requirement, thus allowing the test generation for large VLSI circuits. The algorithms are at the switch level so that general MOS digital designs can be handled, and both stuck-at and transistor faults are handled accurately. The approach was implemented in a hierarchical test generation system, CRIS, that runs under UNIX on SPARC workstations. CRIS was used successfully to generate tests with high fault coverage for large combinational and sequential circuits.< >

关键词： Automatic testing Circuit simulation combinational logic circuits Fault location logic circuit testing Sequential logic circuits Very-large-scale integration

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Optimisation techniques based on the use of genetic algorithms (GAs) for logic implementation on FPGAs

Optimisation techniques based on the use of genetic algorith...

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IEE Colloquium on Software Support and CAD Techniques for FPGAs,

作者： P. Thomson J.F. Miller EECE Department Napier University Edinburgh UK

The work described in this paper began some time ago as an investigation into two problems associated with logic minimisation or optimisation. These are respectively, the state assignment problem in the design of finite state machines, and the optimisation of combinational logic circuits using Reed-Muller (RM) techniques. When faced with such designs, the use of FPGAs to implement circuits is clearly appropriate. However, because of the limited resources available on FPGA parts, in terms of the number of available CLBs, and the increased difficulty that place and route software will experience in the layout of increasingly complex designs, it is felt that some form of optimisation of the design before implementation is still a necessary stage in the design process. This paper describes the implementation of algorithms which attempt to provide this type of optimisation for the two previously mentioned problems. The resultant software uses genetic algorithms to select, breed and test the fitness of potential solutions, and thereby recommend a near-optimal solution. In practice, these recommended solutions represent a considerable saving (in terms of gate count) on many circuit implementations, as experimental results demonstrate.< >

关键词： Circuit optimization combinational logic circuits Field programmable gate arrays Finite state machines Genetic algorithms Design automation Minimization methods Reed-Muller codes State assignment

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A VPI-based combinational IP core module-based mixed level serial fault simulation and test generation methodology

A VPI-based combinational IP core module-based mixed level s...

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Asian Test Symposium (ATS)

作者： Riahi Navabi Lombardi Electrical and Computer Engineering Department North Eastern University USA

In this paper we are presenting a test methodology for performing module-bused mixed level fault simulation and test generation on System-on-Chip (SOC) combinational Intellectual Property (IP) cores for which both a pre-synthesis behavioral description and a post-synthesis netlist is available but in an analyzer output intermediate format not readable by core integraters. We use the Verilog Procedural Interface (VPI) to access and perform serial fault simulation on a pre-compiled core available as a mixed behavioral structural level design. We also use VPI to prepare a testbench environment for performing random pattern test generation. The simulation time results of applying this VPI-based test methodology on ISCAS85 Verilog benchmarks are also presented and compared to the flat (non-mixed level) version the proposed VPI-based environment.

关键词： Hardware design languages Integrated circuit testing logic circuit testing combinational logic circuits

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An enhanced test generator for capacitance induced crosstalk delay faults

An enhanced test generator for capacitance induced crosstalk...

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Asian Test Symposium (ATS)

作者： Sinha Gupta Breuer Department Of Electrical Engineering-Systems University of Southern California Los Angeles USA

Capacitive crosstalk can give rise to slowdown of signals that can propagate to a circuit output and create a functional error A test generation methodology, called XGEN, was developed to generate tests for such failures. Two drawbacks of XGEN are: (i) it is not complete because of restricted propagation conditions, and (ii) a constrained logic value system is used. In this paper, we relax the propagation conditions to increase the solution space. This increases the likelihood of finding a test. We also present a nine-valued algebra that distinguishes between hazardous values and non-hazardous values. Finally, we use the relation between arrival time and required time ranges to selectively turn off the timing computation procedure which is computationally expensive. Other drawbacks of previous versions of XGEN are: (i) a simplified pin-to-pin delay model was used, and (ii) crosstalk computation could not handle timing ranges. We have addressed both of those issues.

关键词： logic circuit testing Crosstalk Capacitance Timing Tree searching combinational logic circuits

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