A compaction algorithm is presented that compacts LSI cell layout in a probabilistic manner. The algorithm is based on the constraint graph where the edge length is iteratively changed probabilistically using paramete...
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A compaction algorithm is presented that compacts LSI cell layout in a probabilistic manner. The algorithm is based on the constraint graph where the edge length is iteratively changed probabilistically using parameters and random numbers. Some experimental results show that an area reduction of from 2% to 20% can be achieved in comparison with the conventional compaction algorithm. The algorithm can also control the aspect ratio of the compacted layout.
In this paper, a new incremental algorithm for layout compaction is proposed. In addition to its linear time performance in terms of the number of rectangles in the layout, we also describe how incremental compaction ...
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In this paper, a new incremental algorithm for layout compaction is proposed. In addition to its linear time performance in terms of the number of rectangles in the layout, we also describe how incremental compaction can form a good feature in the design of a layout editor. The design of such an editor is also described. In the design of the editor, we describe how arrays can be used to implement quadtrees that represent VLSI layouts. Such a representation provides speed of data access and low storage requirements.
A microcode compaction algorithm based on a new description of microoperations and microinstructions is proposed. The technique is independent of the target machine since it does not refer to any machine timing descri...
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A microcode compaction algorithm based on a new description of microoperations and microinstructions is proposed. The technique is independent of the target machine since it does not refer to any machine timing description. It is assumed that the microprogram is described via a high-level microprogramming language. The compaction algorithm is described in terms of operations on the sets of source and destination resources for each microcode block. Some evaluations are made concerning the efficiency of the automatically generated microcode with respect to an increasing microprogram complexity.
A new test set compaction method that uses multiple frame vectors to test fully scanned sequential circuits is proposed. The PAN algorithm is extended to generate compact multiple frame test vectors. The proposed meth...
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A new test set compaction method that uses multiple frame vectors to test fully scanned sequential circuits is proposed. The PAN algorithm is extended to generate compact multiple frame test vectors. The proposed method generates the smallest test sets among all recognised full scan test set compaction algorithms.
In real-domain problems, having generated a complete map for a given problem, a Learning Classifier System needs further steps to extract minimal and representative rules from the original generated ruleset. In an att...
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In real-domain problems, having generated a complete map for a given problem, a Learning Classifier System needs further steps to extract minimal and representative rules from the original generated ruleset. In an attempt to understand the generated rules and their complex underlying knowledge, a new rule-driven approach is introduced which utilizes a quality-based clustering technique to generate clusters of rules. Two main outputs are extracted from each cluster: (1) an aggregate average rule which represents the common features of the group of rules, and (2) an aggregate definite rule which presents the common characteristics within the cluster. Initial experimental results show that these extracted patterns are able to classify future domain cases efficiently.
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