The article proposes a method for reducing the number of LUT elements in the circuit of a compositional microprogram control unit (CMCU) with code sharing. The method is based on the two-fold encoding of operator line...
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The article proposes a method for reducing the number of LUT elements in the circuit of a compositional microprogram control unit (CMCU) with code sharing. The method is based on the two-fold encoding of operator linear chains (OLC). Each chain has a code as an element of the OLC set and as a class element of this set. This approach allows obtaining a two-level microinstruction addressing unit. The control memory of the CMCU is implemented in the embedded memory blocks. The article considers an example of synthesis and provides an analysis of the proposed method.
The paper presents new research results of synthesis of compositional microprogram control unit with extended microinstruction format. The method is addressed for programmable logic devices such as CPLD and FPGA and i...
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ISBN:
(纸本)9788392875604
The paper presents new research results of synthesis of compositional microprogram control unit with extended microinstruction format. The method is addressed for programmable logic devices such as CPLD and FPGA and it is oriented on reduction of hardware amount of CMCU addressing circuit. The reduction is reached due to decrease of the number of terms in system of Boolean functions describing the addressing circuit. The research results shows that application of the method for tested GSAs gives on average 50% decrease of hardware amount and 30% decrease of cycle time when compared to CMCU base structure.
This paper presents results of decreasing hardware resources usage for compositional microprogram control units with code sharing and elementary operational linear chains. Two types of microprogramcontrolunits are c...
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This paper presents results of decreasing hardware resources usage for compositional microprogram control units with code sharing and elementary operational linear chains. Two types of microprogramcontrolunits are compared: a structure with address converter and without it. For synthesis and implementation of the microprogramcontrolunit Xilinx ISE 8.2i package was used. Four optimization strategies available in the ISE package have been applied. The test results show that for some examples memory consumption drops even by 50% in comparison to the implementation without the address converter. It's important to notice that adding an additional block (address converter) to the microprogramcontrolunit does not cause an increase in hardware resource use.
A method for reducing hardware expenses in compositional microprogram control unit and CPLD chips is proposed. This method is based on the use of pseudoequivalent operational linear chains, wide fan-in of PAL macrocel...
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A method for reducing hardware expenses in compositional microprogram control unit and CPLD chips is proposed. This method is based on the use of pseudoequivalent operational linear chains, wide fan-in of PAL macrocells, and existence of free outputs of embedded memory block in CPLD chips. An example of applying the method is given. It is shown that the method reduces hardware expenses to 30%.
This article proposes two modifications of the microcommand addressing system in a compositional microprogram control unit with code sharing. The modifications are based on using FSM pseudoequivalent states to reduce ...
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This article proposes two modifications of the microcommand addressing system in a compositional microprogram control unit with code sharing. The modifications are based on using FSM pseudoequivalent states to reduce the number of rows in the FSM transition table and thereby to reduce the complexity of the combinational part of the device. Methods are proposed for synthesizing compositionalcontrolunits with a modified microcommand addressing system. The research results are presented and appropriate fields of application of the methods proposed are considered.
The joint use of structural decomposition and code conversion is proposed. The method is oriented to reducing the hardware in compositional microprogram control units. This reduction is due to the decrease in the numb...
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The joint use of structural decomposition and code conversion is proposed. The method is oriented to reducing the hardware in compositional microprogram control units. This reduction is due to the decrease in the number of arguments for irregular functions and in the number of the functions themseves. Embedded memory blocks are used to implement regular functions. Design methods and an example are discussed. Experimental results are given.
Two methods are proposed for microinstruction addressing in interpreting a control algorithm by a compositional microprogram control unit (CMCU). The method of refined addressing allows one to uniquely identify output...
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Two methods are proposed for microinstruction addressing in interpreting a control algorithm by a compositional microprogram control unit (CMCU). The method of refined addressing allows one to uniquely identify outputs of operational linear chains (OLCs) using a minimal number of address bits. The method of optimal addressing makes it possible to represent classes of pseudoequivalent OLCs using a minimal number of generalized intervals of the code space. The proposed methods are illustrated by examples. Both methods make it possible to reduce the number of look-up table (LUT) elements in a CMCU logic circuit in comparison with its base structure. In the majority of cases, the clock period decreases with decreasing the amount of hardware.
The method of optimal addressing of microinstructions of CMCU with mutual memory is proposed. The method is based on the effective encoding of classes of the pseudo-equivalent operational linear chains. An example of ...
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ISBN:
(纸本)9789665335870
The method of optimal addressing of microinstructions of CMCU with mutual memory is proposed. The method is based on the effective encoding of classes of the pseudo-equivalent operational linear chains. An example of application of proposed method is shown.
Two methods are proposed targeted at reduction in the number of look-up table elements in logic circuits of compositional microprogram control units (CMCUs) with code sharing. The methods assume the application of fie...
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Two methods are proposed targeted at reduction in the number of look-up table elements in logic circuits of compositional microprogram control units (CMCUs) with code sharing. The methods assume the application of field-programmable gate arrays for the implementation of the combinational part of the CMCU, whereas embedded-memory blocks are used for implementation of its control memory. Both methods are based on the existence of classes of pseudoequivalent operational linear chains in a microprogram to be implemented. Conditions for the application of the proposed methods and examples of design are shown. Results of conducted experiments are given.
The method of optimization of amount of PAL macrocells in the circuit of compositional microprogram control units proposed. The method is based on introducing of additional microinstructions with codes of the classes ...
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ISBN:
(纸本)9789531841306
The method of optimization of amount of PAL macrocells in the circuit of compositional microprogram control units proposed. The method is based on introducing of additional microinstructions with codes of the classes of pseudoequivalent operational linear chains. The proposed method is based on usage of natural redundancy of embedded memory blocks that are used to implement the control memory. An example of application of proposed method is given.
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