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Survey of Inter-Prediction Methods for Time-Varying Mesh compression

COMPUTER GRAPHICS FORUM 2025年第1期44卷

作者： Dvorak, Jan Hacha, Filip Arvanitis, Gerasimos Podgorelec, David Moustakas, Konstantinos Vasa, Libor Univ West Bohemia Pilsen Fac Appl Sci Dept Comp Sci & Engn Plzen Czech Republic Univ Patras Dept Elect & Comp Engn Patras Greece Univ Maribor Fac Elect Engn & Comp Sci Maribor Slovenia

Time-varying meshes (TVMs), that is mesh sequences with varying connectivity, are a greatly versatile representation of shapes evolving in time, as they allow a surface topology to change or details to appear or disappear at any time during the sequence. This, however, comes at the cost of large storage size. Since 2003, there have been attempts to compress such data efficiently. While the problem may seem trivial at first sight, considering the strong temporal coherence of shapes represented by the individual frames, it turns out that the varying connectivity and the absence of implicit correspondence information that stems from it makes it rather difficult to exploit the redundancies present in the data. Therefore, efficient and general TVM compression is still considered an open problem. We describe and categorize existing approaches while pointing out the current challenges in the field and hint at some related techniques that might be helpful in addressing them. We also provide an overview of the reported performance of the discussed methods and a list of datasets that are publicly available for experiments. Finally, we also discuss potential future trends in the field.

关键词： compression algorithms data compression modelling polygonal mesh reduction

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A Low-Complexity and High-Throughput Hardware Design for Lempel-Ziv 4 compression Algorithm

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2025年

作者： Chen, Tao Song, Suwen Wang, Zhongfeng Nanjing Univ Sch Elect Sci & Engn Nanjing 210023 Peoples R China Sun Yat Sen Univ Sch Integrated Circuits Shenzhen 518107 Peoples R China

The Lempel-Ziv (LZ) 4 compression algorithm, widely used in data transmission and storage, faces the challenge of high-speed implementation and increased complexity in the era of big data. Therefore, this paper proposes a single-core parallel architecture for LZ4 algorithm with high throughput and low complexity. Firstly, to enhance throughput, two innovative approaches are introduced from the perspective of parallelism and frequency with an acceptable compression ratio loss: each parallelization window is restricted to performing a single match, bridging the gap between actual and theoretical parallelism;the feedback loop in the circuit is broken by utilizing the spatial correlation between adjacent matches for higher frequency. Secondly, two optimization schemes are employed on resource-consuming modules to achieve low complexity. Multi-port hash tables using Live Value Table (LVT) are improved based on inherent data characteristics, significantly reducing the hardware resource consumption while ensuring excellent scalability on hash table depth and frequency. The match comparison operation is moved ahead, further reducing the logic resources by 64.36%. Finally, our design is implemented on FPGA and ASIC platforms. Experimental results on FPGA demonstrate that the proposed architecture achieves a throughput of 17.39 Gb/s, exhibiting a 2.86x improvement over the state-of-the-art, along with a 6.46x enhancement in area efficiency. Further optimizations including Canonic Signed Digit (CSD) coding and computational reuse on the ASIC platform result in a 45x improvement in area efficiency.

关键词： Hardware Throughput Parallel processing Complexity theory Field programmable gate arrays compression algorithms Encoding Signal processing algorithms Parallel architectures Logic Lossless data compression LZ4 algorithm FPGA ASIC high throughput low complexity hardware accelerator

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Can Image compression Rely on CLIP?

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IEEE ACCESS 2024年 12卷 78922-78938页

作者： Bachard, Tom Maugey, Thomas Univ Rennes Inria IRISA Campus Beaulieu F-35042 Rennes France

Coding algorithms are usually designed to faithfully reconstruct images, which limits the expected gains in compression. A new approach based on generative models allows for new compression algorithms that can reach drastically lower compression rates. Instead of pixel fidelity, these algorithms aim at faithfully generating images that have the same high-level interpretation as their inputs. In that context, the challenge becomes to set a good representation for the semantics of an image. While text or segmentation maps have been investigated and have shown their limitations, in this paper, we ask the following question: do powerful foundation models such as CLIP provide a semantic description suited for compression? By suited for compression, we mean that this description is robust to traditional compression tools and, in particular, quantization. We show that CLIP fulfills semantic robustness properties. This makes it an interesting support for generative compression. To make that intuition concrete, we propose a proof-of-concept for a generative codec based on CLIP. Results demonstrate that our CLIP-based coder beats state-of-the-art compression pipelines at extremely low bitrates (0.0012 BPP), both in terms of image quality (65.3 for MUSIQ) and semantic preservation (0.86 for the Clip score).

关键词： Semantics Image coding Vectors Measurement Pipelines Image segmentation Atmospheric modeling compression algorithms deep learning image coding image processing image reconstruction image representation semantic

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CStream: Parallel Data Stream compression on Multicore Edge Devices

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IEEE TRANSACTIONS ON KNOWLEDGE AND DATA ENGINEERING 2024年第11期36卷 5889-5904页

作者： Zeng, Xianzhi Zhang, Shuhao Singapore Univ Technol & Design Singapore 487372 Singapore Nanyang Technol Univ Singapore 639798 Singapore

In the burgeoning realm of Internet of Things (IoT) applications on edge devices, data stream compression has become increasingly pertinent. The integration of added compression overhead and limited hardware resources on these devices calls for a nuanced software-hardware co-design. This paper introduces CStream, , a pioneering framework crafted for parallelizing stream compression on multicore edge devices. CStream grapples with the distinct challenges of delivering a high compression ratio, high throughput, low latency, and low energy consumption. Notably, CStream distinguishes itself by accommodating an array of stream compression algorithms, a variety of hardware architectures and configurations, and an innovative set of parallelization strategies, some of which are proposed herein for the first time. Our evaluation showcases the efficacy of a thoughtful co-design involving a lossy compression algorithm, asymmetric multicore processors, and our novel, hardware-conscious parallelization strategies. This approach achieves a 2.8x compression ratio with only marginal information loss, 4.3x throughput, 65% latency reduction and 89% energy consumption reduction, compared to designs lacking such strategic integration.

关键词： Multicore processing compression algorithms Throughput Energy consumption Program processors Hardware Internet of Things Asymmetric hardware edge computing and IoT stream compression

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Zero and Narrow-Width Value-Aware compression for Quantized Convolutional Neural Networks

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IEEE TRANSACTIONS ON COMPUTERS 2024年第1期73卷 249-262页

作者： Jang, Myeongjae Kim, Jinkwon Nam, Haejin Kim, Soontae Korea Adv Inst Sci & Technol KAIST Sch Comp Daejeon 34141 South Korea

Convolutional neural networks are normally used in systems with dedicated neural processing units for CNN-related computations. For high performance and low hardware overheads, CNN datatype quantization is applied. As an additional optimization, to further reduce DRAM accesses, compression algorithms have been used for CNN data. However, conventional zero value-aware compression algorithms suffer from a reduction in compression ratio with the latest quantized CNNs, owing to the small number of zero values. Moreover, the appropriate zero run-length code width can be changed dynamically based on the CNNs, layers, and quantization datatypes. As another compressible data value for increasing the compression ratio, the latest quantized CNNs have many narrow-width values. Because low-precision quantization reduces the data bit width, CNN data are gathered into a few discrete values and incur a biased data distribution. These discrete values become narrow-width values, and constitute a large proportion of the biased distribution. In this article, we propose an efficient compression algorithm for quantized CNNs, ENCORE, which utilizes variable zero run-length encoding and compresses narrow-width values. With the latest quantized CNNs, ENCORE shows higher compression ratios, 93.55% and 50.85% in Mobilenet v1 and Tiny YOLO v3, respectively, than conventional zero value-aware CNN data compression algorithms.

关键词： Quantization (signal) compression algorithms Codes Encoding Convolutional neural networks Data compression Sparse matrices quantization compression neural processing units

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A Hierarchical Encrypted compression Scheme for Intra-Vehicle Network

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IEEE TRANSACTIONS ON INTELLIGENT TRANSPORTATION SYSTEMS 2025年

作者： Shang, Chao Cao, Jin Li, Zejian Niu, Ben Lam, Kwok-Yan Chi, Chi-Hung Li, Hui Xidian Univ Sch Cyber Engn State Key Lab Integrated Serv Networks Xian 710126 Peoples R China Nanyang Technol Univ Coll Comp & Data Sci Natl Digital Trust Ctr Singapore 639798 Singapore Chinese Acad Sci Inst Informat Engn State Key Lab Informat Secur Beijing 100094 Peoples R China Nanyang Technol Univ Coll Comp & Data Sci Singapore 639798 Singapore Nanyang Technol Univ Natl Digital Trust Ctr Singapore 639798 Singapore

The CAN bus is the most widely used bus for intra-vehicle communication due to its high transmission stability, excellent real-time communication capability, and relatively low cost. As the number of ECUs grows, the CAN bus load increases and thus raises the possibility of data transmission delays and errors. Message compression based on the differential algorithm has been proposed to reduce the CAN bus load. However, current works do not consider the security problems of the CAN bus. Attackers can manage to acquire the original messages before compression and disturb the message statistics to decrease compression rate by injecting malicious frames. In this paper, we propose a secure compression mechanism for the intra-vehicle network, including an improved compression algorithm, a stream key distribution scheme, and a hierarchical encryption scheme. Formal verification results show that the proposed scheme can achieve mutual authentication, message confidentiality and integrity, resist replay attacks, and support secure compression. Evaluations using real vehicle data on 16 MHz boards show the average communication overhead can be reduced by 46.38% compared to the original messages. Performance analysis results show our scheme can reduce computational overhead on compression by 31.82% and 19.43% on decompression compared to related schemes.

关键词： Security Encryption Heuristic algorithms Controller area networks Real-time systems compression algorithms Ethernet Authentication Statistical analysis Sorting Intra-vehicle network CAN bus compression authentication encryption security

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Huffman Deep compression of Edge Node Data for Reducing IoT Network Traffic

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IEEE ACCESS 2024年 12卷 122988-122997页

作者： Said Nasif, Ammar Ali Othman, Zulaiha Samsiah Sani, Nor Kamrul Hasan, Mohammad Abudaqqa, Yousra Univ Kebangsaan Malaysia Fac Informat Sci & Technol Res Ctr Artificial Intelligent Technol Bangi 43600 Selangor Malaysia Univ Kebangsaan Malaysia Fac Informat Sci & Technol Res Ctr Cyber Secur Bangi 43600 Selangor Malaysia

Data compression at the Internet of Things (IoT) edge node aims to minimize data traffic in smart cities. The traditional Huffman Coding Algorithm (HCA) is shown as the most effective compression algorithm for sensor data. However, implementing the algorithm at IoT edge nodes is hindered due to memory limitations;HCA requires a large amount of memory to construct a Huffman tree to compress data. To address this issue, this paper proposes a new lossless Huffman Deep compression (HDC) algorithm that incorporates the sliding window technique to fit in memory, reduces the complexity of the Huffman tree using deep learning pruning and pooling techniques, and uses pattern matching with pattern weights instead of using symbol matching and symbol frequencies in HCA. This paper introduces a sliding window approach to minimize memory usage, leveraging pattern matching and weights for higher compression and employing deep learning techniques to reduce the Huffman tree size through pruning and pooling. Experiments were performed using the Esp8266 MCU IoT node on eight numerical attributes from sensors of six of Malaysia's air pollution station datasets. The findings demonstrate that the HDC algorithm has substantially reduced data size (p-value<0.0005), achieving a higher compression ratio (CR) by 1.4x while reducing data size by up to 59%. Furthermore, this achievement is attained while utilizing less than 80 KB of IoT memory and consuming at most 44 mAmps per slide compression. Moreover, the compression performance correlated linearly with the number of patterns in each sliding window. With such excellent performance, using HDC at IoT edge is a considerable solution to reduce the smart-cities network traffic.

关键词： Internet of Things Entropy Random access memory Symbols Deep learning compression algorithms Wireless sensor networks Smart cities Data compression Traffic control compression data traffic deep learning IoT IoT edge node IoT network pooling pruning sensor smart city WSN

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A General Analytical Model for Spatial and Temporal Performance of Bitmap Index compression algorithms in Big Data

A General Analytical Model for Spatial and Temporal Performa...

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International Conference on Computer Communications and Networks (ICCCN)

作者： Yinjun Wu Zhen Chen Yuhao Wen Junwei Cao Wenxun Zheng Ge Ma Research Institute of Information Technology Information Science and Technologies (TNList) Beijing China

Bitmap indexing is flexible to conduct boolean operations in data retrieval. Besides, the query processing based on bitmap indexing is also very fast. Therefore it has been widely used in various big data analytics platforms, such as Druid and Spark etc. However, bitmap index can consume a large amount of memory, which leads to the invention of different kinds of bitmap index compression algorithms without sacrificing temporal performance. In practice, we are often discommoded by choosing a proper algorithm when handling specific problems. Besides, after devising a new algorithm that may outperform existing ones, it is essential to evaluate its performance in theory. Without appropriate theoretical analysis, the deficit of a new algorithm can only be spotted until final experimental results are drawn, thus wasting much time and effort. In this paper, we propose a general analytical model to analyze both the spatial and temporal performance for bitmap index compression algorithms, which can be applied to analyze all kinds of algorithms derived from WAH (word-aligned hybrid). In this model, two types of distributed bitmaps, uniformly distributed bitmaps and clustered bitmaps, are used separately. In order to illustrate this model, several bitmap index compression algorithms are analyzed and compared with each other. algorithms herein are COMBAT (COMbining Binary And Ternary encoding), SECOMPAX (Scope Extended COMPAX) and CONCISE (Compressed 'n' Composable Integer Set), which are all derived from WAH. Evaluation results by MATLAB simulation about these algorithms are also presented. This paper paves the way for further researches on the performance evaluation of various bitmap index compression algorithms in the future.

关键词： Indexes Probability Mathematical model compression algorithms Encoding Analytical models Algorithm design and analysis

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Hardware-Accelerated Kernel-Space Memory compression Using Intel QAT

IEEE COMPUTER ARCHITECTURE LETTERS

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IEEE COMPUTER ARCHITECTURE LETTERS 2025年第1期24卷 57-60页

作者： Xia, Qirong Ji, Houxiang Zhou, Yang Kim, Nam Sung Univ Illinois Urbana IL 61801 USA

Data compression has been widely used by datacenters to decrease the consumption of not only the memory and storage capacity but also the interconnect bandwidth. Nonetheless, the CPU cycles consumed for data compression notably contribute to the overall datacenter taxes. To provide a cost-efficient data compression capability for datacenters, Intel has introduced QuickAssist Technology (QAT), a PCIe-attached data-compression accelerator. In this work, we first comprehensively evaluate the compression/decompression performance of the latest on-chip QAT accelerator and then compare it with that of the previous-generation off-chip QAT accelerator. Subsequently, as a compelling application for QAT, we take a Linux memory optimization kernel feature: compressed cache for swap pages (zswap), re-implement it to use QAT efficiently, and then compare the performance of QAT-based zswap with that of CPU-based zswap. Our evaluation shows that the deployment of CPU-based zswap increases the tail latency of a co-running latency-sensitive application, Redis by 3.2-12.1x, while that of QAT-based zswap does not notably increase the tail latency compared to no deployment of zswap.

关键词： System-on-chip Throughput Kernel Linux compression algorithms Benchmark testing Support vector machines Huffman coding Heuristic algorithms Translation Data compression hardware accelerator operating system

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Marmotini: A Weight Density Adaptation Architecture With Hybrid compression Method for Spiking Neural Network

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2024年第12期32卷 2293-2302页

作者： Wang, Zilin Zhong, Yi Ou, Zehong Yang, Youming Feng, Shuo Chen, Guang Cui, Xiaoxin Jia, Song Wang, Yuan Peking Univ MPW Ctr Sch Integrated Circuits Key Lab Microelect Devices & Circuits Beijing 100871 Peoples R China Peking Univ Sch Software & Microelect Beijing 102600 Peoples R China Peking Univ Beijing Adv Innovat Ctr Integrated Circuits Beijing 100871 Peoples R China

Brain-inspired spiking neural network (SNN) has recently attracted widespread interest owing to its event-driven nature and relatively low-power hardware for transmitting highly sparse binary spikes. To further improve energy efficiency, some matrix compression algorithms are used for weight storage. However, the weight sparsity of different layers varies greatly. For a multicore neuromorphic system, it is difficult for the same compression algorithm to adapt to all the layers of SNN model. In this work, we propose a weight density adaptation architecture with hybrid compression method for SNN, named Marmotini. It is a multicore heterogeneous design, including three types of cores to complete computation of different weight sparsity. Benefiting from the hybrid compression method, Marmotini minimizes the waste of neurons and weights as much as possible. Besides, for better flexibility, a reconfigurable core that can be configured to compute convolutional layer or fully connected layer is proposed. Implemented on Xilinx Kintex UltraScale XCKU115 field-programmable gate array (FPGA) board, Marmotini can operate at 150-MHz frequency, achieving 244.6-GSOP/s peak performance and 54.1-GSOP/W energy efficiency at 0% spike sparsity.

关键词： Multicore processing Neurons Computer architecture compression algorithms Indexes Convolution Synapses Convolutional neural network field-programmable gate array (FPGA) neuromorphic computing spiking neural network (SNN)

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