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Specific ADC of NVM-Based computation-in-memory for Deep Neural Networks

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2024年第12期71卷 5387-5399页

作者： Shi, Ao Zhang, Yizhou Han, Lixia Zhou, Zheng Chen, Yiyang Yang, Haozhang Liu, Lifeng Shen, Linxiao Liu, Xiaoyan Kang, Jinfeng Huang, Peng Peking Univ Sch Integrated Circuits Beijing 100871 Peoples R China Beijing Adv Innovat Ctr Integrated Circuits Beijing 100871 Peoples R China

Non-volatile memory (NVM)-based computation-in-memory has demonstrated a significant advantage inhigh-efficiency neural networks. However, the requirement ofanalog-to-digital converter (ADC) and post-processing circuitsnot only cost high energy and area but also results in high com-putation errors, which tradeoffs the performance boost broughtby CIM. Here, we present a specific ADC and post-processingcircuit of the NVM-based CIM neural network to address theseissues. The main contributions include: (1) A novel residualcharge accumulation function (RCA) is designed to achievecharge-domain summation of quantized partial sum and reduces38% quantization error;(2) Charge reset is introduced in theintegrate & fire circuit to realize<1 LSB INL at +/- 7 bits and aspeed of 285MHz/LSB;(3) Sample & hold, current subtraction,and bidirectional counter are designed to improve 3.95xenergyefficiency and 2.48xarea efficiency. Evaluation based on themeasured results of the fabricated chip shows that the VGG-11neural network with the proposed ADC circuit can achieve a3.28-time improvement in energy efficiency while maintainingthe same network recognition rate

关键词： Circuits Neural networks Quantization (signal) Sensors Nonvolatile memory Virtual machine monitors Common Information Model (computing) computation in memory deep neural network ADC

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Reliability analysis and mitigation for analog computation-in-memory: from technology to application 42

Reliability analysis and mitigation for analog computation-i...

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42nd VLSI Test Symposium (VTS)

作者： Mayahinia, Mahta Hezayyin, Haneen G. Tahoori, Mehdi Karlsruhe Inst Technol KIT Dept Comp Sci Karlsruhe Germany

ISBN: (纸本)9798350363784;9798350363791

The computation-in-memory (CiM) paradigm is widely acknowledged to tackle the memory wall problem. Additionally, leveraging non-volatile resistive memory (NVM) technologies enhances the energy efficiency of the CiM by enabling analog computation. However, the reliability of the NVM-CiM is challenged due to the inherent device and circuit imperfections, the technology-level process variation, the sensing offset, and the analog nature of the computation. In this paper, we perform comprehensive reliability analysis and mitigation from the technology all the way to the CiM application. For this aim, we accurately model the NVM device variability and imperfection and effectively model the consequent errors at the circuit level by considering crossbar parasitic and sensing offset. Subsequently, we inject these modeled faults into the CiM-enabled full-system architecture. The study quantitatively assesses the masking capability of CiM applications and explores potential mitigation techniques to enhance the overall reliability of NVM-CiM.

关键词： computation in memory Reliability Non-volatile resistive memories Analog computing Fault injection Masking Interconnect dominance

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Low Quantization Error Readout Circuit with Fully Charge-Domain Calculation for computation-in-memory Deep Neural Network

Low Quantization Error Readout Circuit with Fully Charge-Dom...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Shi, Ao Zhang, Yizhou Han, Lixia Zhou, Zheng Chen, Yiyang Liu, Lifeng Shen, LinXiao Huang, Peng Liu, Xiaoyan Kang, Jinfeng Peking Univ Sch Integrated Circuits Beijing 100871 Peoples R China Beijing Adv Innovat Ctr Integrated Circuits Beijing 100871 Peoples R China

ISBN: (纸本)9798350330991;9798350331004

This work presents a low quantization error readout circuit with fully-charge-domain calculation for quantization and post-process of computation-in-memory (CIM)-based neural network. The contributions include: (1) A novel residual charge accumulation function is designed to achieve charge-domain summation of quantized partial sum, and reduces 38% quantization error;(2) Charge reset is introduced in the integrate & fire circuit to realize <1 LSB INL at +/- 7 bits and speed of 285MHz/LSB;(3) Sample & hold, current subtraction and bidirectional counter are designed to improve 3.95x energy efficiency and 2.48x area efficiency.

关键词： computation in memory ADC deep neural network

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SieveMem: A computation-in-memory Architecture for Fast and Accurate Pre-Alignment 34

SieveMem: A Computation-in-Memory Architecture for Fast and ...

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34th IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP)

作者： Shahroodi, Taha Miao, Michael Zahedi, Mahdi Wong, Stephan Hamdioui, Said Delft Univ Technol Dept Quantum & Comp Engn Delft Netherlands

ISBN: (纸本)9798350346855

The high execution time of DNA sequence alignment negatively affects many genomic studies that rely on sequence alignment results. Pre-alignment filtering was introduced as a step before alignment to reduce the execution time of short-read sequence alignment greatly. With its success, i.e., achieving high accuracy and thus removing unnecessary alignments, the filtering itself now constitutes the larger portion of the execution time. A significant contributing factor entails the movement of sequences from the memory to the processing units, while a majority will filter out as they do not result in an acceptable alignment. State-of-the-art (SotA) pre-alignment filtering accelerators suffer from the same overhead for data movements. Furthermore, these accelerators lack support for future pre-alignment filtering algorithms using the same operations and underlying hardware. This paper addresses these shortcomings by introducing SieveMem. SieveMem is an architecture that exploits the computation-in-memory paradigm with memristive-based devices to support shared kernels of pre-alignment filters and algorithms inside the memory (i.e., preventing data movements). SieveMem architecture also provides support for future algorithms. SieveMem supports more than 47.6% of shared operations among all top 5 SotA filters. Moreover, SieveMem includes a hardware-friendly pre-alignment filtering algorithm called BandedKrait, inspired by a combination of mentioned kernels. Our evaluations show that SieveMem provides up to 331.1x and 446.8x improvement in the execution time of the two most-common kernels. Our evaluations also show that BandedKrait provides accuracy at the SotA level. Using BandedKrait on SieveMem, a design we call Mem-BandedKrait, one can improve the execution time of end-to-end sequence alignment irrespective of the dataset, which can go up to 91.4x compared to the SotA accelerator on GPU.

关键词： Alignment Pre-alignment Filter computation in memory Emerging memory Technology Hardware Accelerator

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System Simulation of Memristor Based computation in memory Platforms 1

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20th International Conference on Embedded Computer Systems - Architectures, Modeling, and Simulation (SAMOS)

作者： BanaGozar, Ali Vadivel, Kanishkan Multanen, Joonas Jaaskelainen, Pekka Stuijk, Sander Corporaal, Henk Eindhoven Univ Technol Eindhoven Netherlands Tampere Univ Tampere Finland

ISBN: (数字)9783030609399

ISBN: (纸本)9783030609399;9783030609382

Processors based on the von Neumann architecture show inefficient performance on many emerging data-intensive workloads. computation in-memory (CIM) tries to address this challenge by performing the computation on the data location. To realize CIM, memristors, that are deployed in a crossbar structure, are a promising candidate. Even though extensive research has been carried out on memristors at device/circuit-level, the implications of their integration as accelerators (CIM units) in a full-blown system are not studied extensively. To study that, we developed a simulator for memristor crossbar and its analog peripheries. This paper evaluates a complete system consisting of a Transport Triggered Architecture (TTA) based host core integrating one or more CIM units. This evaluation is based on a cycle-accurate simulation. For this purpose we designed a simulator which a) includes the memristor crossbar operations as well as its surrounding analog drivers, b) provides the required interface to the co-processing digital elements, and c) presents a micro-instruction set architecture (micro-ISA) that controls and operates both analog and digital components. It is used to assess the effectiveness of the CIM unit in terms of performance, energy, and area in a full-blown system. It is shown, for example, that the EDAP for the deep learning application, LeNet, is reduced by 84% in a full-blown system deploying memristor based crossbars.

关键词： computation in memory Memristor Simulator Non-von neumann architectures Transport Triggered Architecture

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A Fast Half Adder using 8T SRAM for computation-in-memory

A Fast Half Adder using 8T SRAM for Computation-in-Memory

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IEEE International Conference on Consumer Electronics-Asia (ICCE-Asia)

作者： Han, Jaehyeon Kim, Youngmin Hongik Univ Sch Elect & Elect Engn Seoul South Korea

ISBN: (纸本)9781665408578

The conventional Von Neumann computing architecture faces limitation as data intensive applications have increased. To solve the problem, the new computing platform "computation-in-memory" has been introduced. In this study, a new design of the half adder implemented in memory array using 8T static random-access memory (SRAM) and latch-type sense amplifier is proposed. This design uses four logic gates to implement a half adder. It reduces time delay of getting the final value by 33% compared to the former architecture of the half adder which uses five logic gates.

关键词： Half Adder computation in memory Processing in memory SRAM

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An Area-Efficient and Robust Memristive LUT Based on the Enhanced Scouting Logic Cells

An Area-Efficient and Robust Memristive LUT Based on the Enh...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Cui, Xiaole Liu, Fan Zhang, Sunrui Cui, Xiaoxin Peking Univ Key Lab Integrated Microsyst Shenzhen Grad Sch Shenzhen 518055 Peoples R China Peking Univ Inst Microelect Beijing 100871 Peoples R China Peng Cheng Lab Shenzhen 518055 Peoples R China

ISBN: (纸本)9781665484855

The resistive random access memory (RRAM) is a two-terminal device, which represents logic states with its different resistance states. The RRAM devices were applied to the Look-Up Table (LUT) in recent years. However, the RRAM based logic circuits are affected by the resistance variation of the RRAM devices. This work proposes a memristive LUT scheme based on the enhanced scouting logic (ESL) cells, to address this challenge. The read-write separation feature of the ESL cell is applied to reduce the number of working cycles of the proposed LUT circuit. The Monte Carlo simulation results show that the proposed LUT scheme has the small standard deviation. And the proposed LUT has relatively small area and high performance.

关键词： Resistive Random Access memory Look-Up Table computation in memory Enhanced Scouting Logic

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SACA: System-level Analog CIM Accelerators Simulation Framework: Architecture and Cycle-accurate System-to-device Simulator 37

SACA: System-level Analog CIM Accelerators Simulation Framew...

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37th Conference on Design of Circuits and Integrated Circuits (DCIS)

作者： Vadivel, Kanishkan Garcia-Redondo, Fernando BanaGozar, Ali Corporaal, Henk Das, Shidhartha TU Eindhoven Eindhoven Netherlands Arm Ltd Cambridge England

ISBN: (数字)9781665459501

ISBN: (纸本)9781665459501

Analog computation-In- memory ( CIM) architectures promise to bring to the edge the required compute and memory demands of TinyML applications while consuming extremely low power. However, the analog CIM paradigm is suitable for accelerating vector-matrix multiplication patterns alone, and the accuracy of the computation itself is stirred by the CIM device and its driving circuit non-idealities. Despite these practical constraints, CIM accelerators are often developed and evaluated in isolation without considering real-world system-level conditions, such as sharing system resources (host CPU, mainmemory, and interconnect) for inter-layer pre/post-processing, data alignment, and data movement. These make it challenging to evaluate the energy, performance, area, and accuracy tradeoff for practical, end-to- end applications. To address this, we propose a first SoC level, gemS-based, open-source simulation framework for CIM accelerator design. It supports the modeling of hierarchical CIM accelerators for different device technologies and digital/ mixed-signal driving circuit configurations, along with their non-ideal behaviour. The associated full-stack software provides APls for (re-)configuring the CIM accelerator for offloading computations at the system level. To demonstrate some capabilities of the SACA, we carried out design space exploration on two representative TinyML tasks - Human Activity Recognition and CIFARIO image classification. The results lead to optimal accelerator profiles and indicate a trade- off between the energy, area, performance, and accuracy for different configurations.

关键词： computation in memory CIM gemS PPA

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Analyzing the Electromigration Challenges of computation in Resistive Memories

Analyzing the Electromigration Challenges of Computation in ...

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IEEE International Test Conference (ITC)

作者： Mayahinia, Mahta Tahoori, Mehdi Perumkunnil, Manu Croes, Kristof Catthoor, Francky Karlsruhe Inst Technol Karlsruhe Germany Imec Vzw Leuven Belgium Katholieke Univ Leuven ESAT Leuven Belgium

ISBN: (数字)9781665462709

ISBN: (纸本)9781665462709

Performing the computation in memory (CiM) based on the resistive non-volatile memories can significantly improve the energy efficiency and performance of data-intensive and deep learning applications. Activating multiple rows of the memories at the same time is required in Multiply and Accumulation (MAC) operation of neural networks. This simultaneous activation, however, increases the current density of the shared interconnect, which exacerbates the Electromigration (EM) risk. This paper analyzes the EM phenomenon in CiM-oriented MAC paradigms based on emerging non-volatile resistive memories including Spin Transfer Torque Magnetic RAM (STT-MRAM), Redox-based RAM (ReRAM), and Phase Change memory (PCM). We show how EM is exacerbated compared to normal memory architectures. For EM analysis in CiM, we modify the existing EM models, and consider different interconnect and array dimensions. We also propose the EM-aware row activation pattern as effective means to mitigate the EM degradations in the analog MAC paradigms.

关键词： Electromigration computation in memory Analog computing Emerging non-volatile resistive memories

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NIMBLE: A Neuromorphic Learning Scheme and Memristor Based Computing-in-memory Engine for EMG Based Hand Gesture Recognition

NIMBLE: A Neuromorphic Learning Scheme and Memristor Based C...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Tian, Fengshi Jiang, Jingwen Liang, Jinhao Zhang, Zhiyuan Shi, Jiahe Fang, Chaoming Wu, Hui Xue, Xiaoyong Zeng, Xiaoyang Fudan Univ Sch Microelect State Key Lab ASIC & Syst Shanghai Peoples R China

ISBN: (纸本)9781665484855

EMG based hand gesture recognition on convolutional neural networks (CNNs) has been widely learned, which gains high accuracy. However, CNN based systems are computationally complex and power consuming, thus hard to be deployed at edge. Biologically inspired, a new neuromorphic learning and computing approach for electromyogram (EMG) based hand gesture recognition tasks is proposed in this work. This approach designs an activate and inhibit joint processing spiking neural network (AIPS-SNN) which reaches an accuracy of 85.6% on Nina Pro dataset. Furthermore, the AIPS-SNN is deployed on the proposed memristor based computation in-memory (CIM) system, the power efficiency and area efficiency of which reach 10.146 TOPS/W and 35.399 GOPS/mm2, respectively. The experimental results indicate that the proposed neuromorphic CIM engine is promising for edge deployment.

关键词： Hand gesture recognition EMG neuromorphic spiking neural network memristor computation in memory

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